Engineer, CPU Performance Verification

Georgian; Austin (TX); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a talented engineer to join the CPU design team to drive performance verification and RTL-to-model correlation for a high-performance RISC-V-based CPU.

The role is hybrid, based out of Austin, TX or Santa Clara, CA, with collaboration across core architects and RTL teams to deliver an efficient design and validated performance metrics. Open to multiple seniorities and compensated accordingly.

Qualifications

• Experience analyzing modern CPU performance data and bottlenecks.
• Proficient in C++ and Python; familiar with compilation, simulation, and emulation tools.
• Knowledge of high-performance CPU core architecture and RTL/debugging.

Responsibilities

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
• Draft performance test plans and develop microbenchmarks to exercise features and expose bottlenecks.
• Enhance tools/methodologies for performance analysis and correlation to improve development efficiency.

Skills

C++

Python

RTL debugging

Performance modeling

CPU architecture

Debugging pre-silicon

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V-based CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team to drive performance verification and correlation between RTL and the performance model. You'll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role ishybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Great at identifying problems and developing solutions.
• Experience analyzing modern CPU performance data, identifying bottlenecks and building the tools needed to do it efficiently.
• Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation.
• Knowledgeable in architecture and microarchitecture of high-performance CPU cores.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments.
• Exposure to performance modeling and RTL-to-model correlation.

What We Need

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
• Draft performance testplans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
• Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on experience optimizing CPU designs in both pre-silicon and post-silicon phases.
• Deep familiarity with the performance modeling and RTL simulation/emulation flows used to verify a high-performance CPU.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.