Hybrid RISC-V HPC CPU Verification Lead

Tenstorrent Inc.; United States; Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent Inc. is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high‑performance processors.

The role requires deep CPU verification expertise and the ability to guide large engineering teams from design through tapeout and post‑silicon validation. The position is hybrid, based in Santa Clara, CA or Austin, TX, with offers aligned to experience level and a broad set of verification technologies including simulation, formal methods,

Qualifications

• Verifying high-performance superscalar CPUs, including out-of-order and speculative processors.
• Strong knowledge of RISC-V ISA, privileged architecture, virtual memory and memory model behavior.
• Proficiency in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage and advanced debugging.
• Hands-on experience with CPU reference models, instruction generators or ISS-based checking.
• Expertise with formal verification and large-scale CPU verification environments.

Responsibilities

• Own verification strategy for RISC-V high-performance superscalar CPUs and subsystems.
• Drive verification planning for OOO, speculative, and superscalar microarchitectures.
• Build and scale test plans, coverage, checkers, assertions, scoreboards and constrained-random environments.
• Verify core CPU features including frontend, branch prediction, rename, scheduling, execution, memory ordering, caches, retirement and interrupts.
• Collaborate with architecture, RTL, performance modeling, SoC, firmware, compiler and validation teams while mentoring engineers.

Skills

CPU verification

RISC-V architecture

SystemVerilog

UVM

constrained-random verification

assertions

functional coverage

debug methodologies

formal verification

Job description

Tenstorrent Inc. is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high‑performance processors.

The role requires deep CPU verification expertise and the ability to guide large engineering teams from design through tapeout and post‑silicon validation. The position is hybrid, based in Santa Clara, CA or Austin, TX, with offers aligned to experience level and a broad set of verification technologies including simulation, formal methods,