Remote Formal Verification Engineer for RISC-V CPUs

Tenstorrent; United States; Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Formal Verification Engineer to verify high‑performance RISC‑V CPUs and AI compute platforms. You will develop formal environments, prove properties, and collaborate with CPU architects and RTL designers to uncover corner cases beyond simulation.

The role is remote, based in North America or Spain, and offers opportunities across experience levels with compensation aligned to level during the interview process.

Qualifications

• 6+ years of design/verification experience for CPUs, SoCs, or complex digital designs.
• Hands-on experience with formal verification methodologies and tools, including properties, assertions, assumptions, constraints, and coverage analysis.
• Strong SystemVerilog skills, including writing and debugging SVA.

Responsibilities

• Develop formal verification environments for high-performance RISC‑V CPUs and AI compute platforms.
• Analyze counterexamples, verify RTL behavior, and drive issues to closure with CPU architects and RTL designers.
• Create scalable properties and proofs for complex control logic and microarchitectural blocks.

Skills

SystemVerilog

Formal verification

Python

C/C++

Debugging

SVA

Tools

SVA tools

Job description

Tenstorrent is seeking a Formal Verification Engineer to verify high‑performance RISC‑V CPUs and AI compute platforms. You will develop formal environments, prove properties, and collaborate with CPU architects and RTL designers to uncover corner cases beyond simulation.

The role is remote, based in North America or Spain, and offers opportunities across experience levels with compensation aligned to level during the interview process.