Remote Verification Engineer, High-Performance RISC-V Cores

Tenstorrent; Santa Clara (CA); Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify high‑performance RISC‑V CPU cores. You will collaborate with architects, RTL designers, and software engineers to develop verification strategies, build test benches, and drive issue closure in a hands‑on role.

The position is remote, open to candidates in North America or Spain, with offers aligned to level and experience. Strong SystemVerilog/UVM and C/C++ or Python skills are required, along with 6+ years in CPU

Qualifications

• 6+ years in design verification for CPUs/SoCs/ASICs.
• Strong SystemVerilog and UVM experience with testbenches.
• Proficient in C/C++ or Python and collaboration with RTL teams.

Responsibilities

• Develop verification strategies and test plans for CPUs.
• Build robust test environments and testbenches.
• Uncover corner cases and debug failures in RTL simulations.
• Own portions of the verification effort and drive issues to closure.
• Work closely with CPU architects, RTL designers and software engineers.

Skills

Hands-on verification

Debugging

Root-cause analysis

Ownership of tasks

Cross-functional collaboration

CPU architecture understanding

Tools

SystemVerilog

UVM

Constrained-random testing

Waveform debugging

C/C++

Python

Job description

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify high‑performance RISC‑V CPU cores. You will collaborate with architects, RTL designers, and software engineers to develop verification strategies, build test benches, and drive issue closure in a hands‑on role.

The position is remote, open to candidates in North America or Spain, with offers aligned to level and experience. Strong SystemVerilog/UVM and C/C++ or Python skills are required, along with 6+ years in CPU