RISC-V CPU Intern: Build a High-Performance AI Core

Tenstorrent Unlisted/Referral Jobs; Santa Clara (CA); On-site; USD 69,000 - 96,000; Part time

Benefits offered by this job

Competitive compensation

Job summary

Tenstorrent invites interns to contribute to a high-performance RISC-V CPU project on-site in the United States. You will engage with RTL design, verification, and platform software teams to translate architecture into efficient silicon and software shipping cycles.

Ideal candidates are pursuing a relevant degree with strong coursework in CPU architecture, HDL, and low-level programming, and are eager to learn across RTL, verification, and system software in a collaborative environment.

Qualifications

• Pursuing BS/MS/PhD in EE, ECE, CS, CE or related field.
• Strong academic performance with hands-on coursework, project or work experience.
• Interest in RISC-V, CPU architecture, AI/ML hardware, verification, performance, or low-level software.
• Strong debugging, analytical, communication, and collaboration skills.
• Ability to learn new tools and work in an on-site engineering environment.

Responsibilities

• Assist in RTL design, verification, and platform software tasks.
• Support verification workflows, simulations, and testbenches.
• Contribute to performance analysis and bottleneck identification on CPU designs.
• Collaborate with multi-disciplinary teams across RTL, software, and hardware.

Skills

HDLs (SystemVerilog)

Computer architecture

RTL design & debugging

Assembly

C/C++

Python

Perl

Design verification

Formal analysis

CPU microarchitecture

Out-of-order pipelines

Memory systems

Linux

Git

CI/CD pipelines

Firmware

Low-level system software

Education

Pursuing BS/MS/PhD in EE, ECE, CS, CE or related field

Tools

Git

CI/CD pipelines

Job description

Tenstorrent invites interns to contribute to a high-performance RISC-V CPU project on-site in the United States. You will engage with RTL design, verification, and platform software teams to translate architecture into efficient silicon and software shipping cycles.

Ideal candidates are pursuing a relevant degree with strong coursework in CPU architecture, HDL, and low-level programming, and are eager to learn across RTL, verification, and system software in a collaborative environment.