RISC-V CPU IP Design & Verification Engineer - New Grad

GlobalFoundries; Austin (CA); On-site; USD 86,000 - 170,000; Full time

Job summary

GlobalFoundries seeks a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team and develop and verify advanced RISC-V processor IP. Role includes hands-on work in CPU microarchitecture, SystemVerilog RTL, and functional verification, with opportunities in Austin, Texas or Santa Clara, California.

The position offers exposure to power, performance, and area analysis, automated testing, and collaboration across architecture and verification teams.

Qualifications

• Education: degree in Electrical/Computer Engineering (Bachelor/Master/PhD).
• Minimum GPA 3.0 and good academic standing.
• Fluent English (written & spoken).
• Strong foundation in digital logic design and computer architecture.
• Coursework or projects with Verilog/SystemVerilog.
• Understanding CPU fundamentals: pipelines, execution, memory hierarchy.
• Programming/scripting in Python, C/C++, or similar.

Responsibilities

• Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL design.
• Contribute to CPU functions: fetch/decode, execute, load/store, caches, CSRs, exceptions, interrupts.
• Develop verification tests, assertions, checkers, and coverage for CPU features.
• Run simulations, regressions, and debug using logs and waveforms.
• Support functional/coverage closure through design and verification reviews.
• Support CPU power, performance, and area analysis and optimization.
• Develop automation scripts to improve design, verification, and debugging productivity.

Skills

Digital logic

Computer architecture

Verilog SystemVerilog

Python C/C++ scripting

Debugging

Problem solving

English language

Education

Bachelor's/Master's/PhD in Electrical/Computer Engineering

GPA ≥ 3.0

Tools

SystemVerilog/UVM

Git

Linux

Waveform tools

Job description

GlobalFoundries seeks a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team and develop and verify advanced RISC-V processor IP. Role includes hands-on work in CPU microarchitecture, SystemVerilog RTL, and functional verification, with opportunities in Austin, Texas or Santa Clara, California.

The position offers exposure to power, performance, and area analysis, automated testing, and collaboration across architecture and verification teams.