RISC-V CPU IP Design & Verification Intern

GlobalFoundries inc.; Austin (TX); Vor Ort; USD 28.000 - 55.000; Vollzeit

Zusammenfassung

GlobalFoundries seeks hands-on interns in the MIPS CPU IP Engineering group for design and verification of advanced RISC-V processor IP. You will collaborate with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL, functional verification, performance analysis, automation, and debugging in Austin, TX or Santa Clara, CA.

You will develop verification tests, run simulations, and contribute to CPU feature coverage and debugging, while gaining mentorship and exposure

Qualifikationen

• Education – At least a sophomore pursuing a Bachelor’s, Master’s, or PhD in EE/CE during the internship.
• Must maintain at least a 3.0 GPA and be in good academic standing.
• Fluency in English, written and verbal.
• Able to commit to 40 hours per week during the internship.
• coursework in digital logic design and computer architecture.
• Familiarity with Verilog or SystemVerilog and CPU fundamentals.

Aufgaben

• Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
• Develop verification tests, assertions, checkers, and coverage for CPU features.
• Run simulations, regressions, and debug using logs and waveforms.
• Verify processor functionality across instructions, privilege modes, and memory operations.
• Assist in power, performance, and area analysis and optimization.
• Develop automation in Python/C++ or scripting to enhance productivity.
• Document results and communicate findings to the engineering team.

Kenntnisse

Digital logic design

Computer architecture

Python

C/C++

Verilog/SystemVerilog

Debugging

Analytical skills

Team collaboration

Ausbildung

Bachelor’s/Master’s/PhD in Electrical or Computer Engineering

Sophomore status

Eligible for internship

Tools

SystemVerilog/UVM

Git

Linux

Python scripting

Waveform viewers

Jobbeschreibung

GlobalFoundries seeks hands-on interns in the MIPS CPU IP Engineering group for design and verification of advanced RISC-V processor IP. You will collaborate with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL, functional verification, performance analysis, automation, and debugging in Austin, TX or Santa Clara, CA.

You will develop verification tests, run simulations, and contribute to CPU feature coverage and debugging, while gaining mentorship and exposure