Onsite RISC‑V CPU Internship - RTL/Verification

Tenstorrent; Santa Clara (CA); On-site; USD 69,000 - 96,000; Full time

Job summary

Tenstorrent is seeking interns to contribute to high-performance RISC‑V CPUs. You will work on RTL design, verification, and platform software, gaining hands-on experience with HDL design, CPU architecture, and tooling in a collaborative on-site setting.

Ideal candidates are pursuing BS/MS/PhD in EE, ECE, CS, or CE with hands-on coursework or projects in CPU topics, Linux, and scripting. Roles span multiple sub-teams and locations, including Santa Clara.

Qualifications

• Built a foundation in HDL design and CPU architecture.
• Experience with SystemVerilog, Linux, and version control.
• Hands-on coursework, projects, or work involving RISC‑V/CPU topics.

Responsibilities

• Support RTL design, debug CPU blocks, and contribute to microarchitecture.
• Assist design verification, formal checks, and testbench creation.
• Develop platform software, firmware, and automation for RISC‑V CPUs.
• Contribute to CI/CD pipelines and verification infrastructure.
• Collaborate with on-site teams in Austin, Boston, Fort Collins or Santa Clara.

Skills

HDLs (SystemVerilog)

C/C++

Python

CPU architecture

RISC-V

Debugging & analysis

Linux & Git

Education

Pursuing BS/MS/PhD in EE/ECE/CS/CE

Tools

CI/CD tooling

Job description

Tenstorrent is seeking interns to contribute to high-performance RISC‑V CPUs. You will work on RTL design, verification, and platform software, gaining hands-on experience with HDL design, CPU architecture, and tooling in a collaborative on-site setting.

Ideal candidates are pursuing BS/MS/PhD in EE, ECE, CS, or CE with hands-on coursework or projects in CPU topics, Linux, and scripting. Roles span multiple sub-teams and locations, including Santa Clara.