RISC-V CPU IP Design & Verification Intern

GlobalFoundries inc.; Austin, Santa Clara (TX, CA); On-site; USD 28,000 - 55,000; Full time

Job summary

GlobalFoundries inc. is seeking a CPU IP Design & Verification Intern for Summer 2027 to gain hands-on experience in RISC-V processor development.

You will work with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL implementation, and debugging in Austin, TX or Santa Clara, CA. The role emphasizes Python/C/C++ scripting, test development, and collaboration within a safety-conscious, internship program.

Qualifications

• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with Verilog or SystemVerilog.
• Programming or scripting experience with Python, C/C++, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Responsibilities

• Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
• Develop verification tests, assertions, checkers, and functional coverage for CPU features.
• Run CPU simulations and regressions; debug failures using logs, architectural traces, and waveforms.
• Document technical results and communicate findings to the engineering team.

Skills

Digital logic

Computer architecture

SystemVerilog

Python

C/C++

Debugging

Education

Sophomore standing in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog

Git

Linux

Job description

GlobalFoundries inc. is seeking a CPU IP Design & Verification Intern for Summer 2027 to gain hands-on experience in RISC-V processor development.

You will work with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL implementation, and debugging in Austin, TX or Santa Clara, CA. The role emphasizes Python/C/C++ scripting, test development, and collaboration within a safety-conscious, internship program.