RISC-V CPU Architect/RTL Lead

JDWK Inc.; United States; Remoto; USD 225.000 - 300.000; Tempo pieno

Descrizione del lavoro

JDWK Inc. is seeking a hands-on CPU RTL Lead to own RISC-V core development, from architecture through RTL implementation.

You will evaluate open-source cores and design enhancements for our custom silicon roadmap while leading verification, synthesis, and performance analysis flows in a fast-paced startup. You will collaborate with SoC, memory, and firmware teams to ensure seamless integration and coding standards.

Competenze

• 7+ years of RTL design experience on CPU or DSP projects.
• Deep understanding of CPU microarchitecture, pipelines, hazards, caches and MMUs.
• Strong knowledge of the RISC-V ISA and extensions.
• Hands-on with open-source RISC-V cores such as Rocket, CVA6, Ibex or BOOM.
• Proficiency in SystemVerilog/Verilog RTL design, simulation and synthesis.
• Experience with EDA tools for synthesis and linting.
• Solid verification experience (UVM, formal or constrained-random).
• Strong communication and cross-functional collaboration.

Mansioni

• Own the RISC-V CPU microarchitecture and RTL implementation.
• Evaluate and compare open-source RISC-V cores.
• Architect enhancements or new cores for specific domains.
• Develop and maintain high-quality, synthesizable RTL.
• Define verification strategy with UVM, formal or FPGA-based validation.
• Optimize for PPA targets through microarchitectural tuning.
• Collaborate with SoC, memory, and firmware teams for integration.
• Establish coding standards, linting, and CI for RTL and verification.
• Mentor engineers and help build a small design team.

Conoscenze

RTL design

CPU microarchitecture

RISC-V ISA

Open-source RISC-V

SystemVerilog

EDA tools

Verification methods

Cross-functional

Startup mindset

Mentoring

Strumenti

Synopsys

Cadence

Open-source flows

Descrizione del lavoro

Lead the selection, development, and integration of RISC-V CPU cores

About JDWK Inc.

JDWK was started with the goal of drastically reducing the time and resources needed to design modern VLSI systems through intelligent and highly configurable automation. We work with customers from concept to tapeout to deliver perfect silicon at a fraction of the cost of traditional design services, while continually enhancing and evolving our software to optimize execution.

Description

About Us

We are a small, fast-moving team building RISC-V-based SoCs and developing automation tools that make custom silicon design more accessible. Our mission is to combine deep hardware design expertise with modern software-driven methodologies.

We’re looking for a CPU RTL Lead to take ownership of our RISC-V core development - someone who understands the landscape of open-source CPU designs, knows their strengths and weaknesses, and can architect and implement a world-class custom core optimized for our application and toolchain goals.

Role Overview

As the CPU RTL Lead , you’ll drive the design and implementation of a RISC-V processor core - from high-level architecture through synthesizable RTL. You will evaluate existing open-source cores, define architectural tradeoffs, and implement new features or custom extensions as needed. You’ll also establish and oversee verification, synthesis, and performance analysis flows for the CPU subsystem.

This role combines hands-on RTL design , microarchitecture definition , and technical leadership in a startup setting where your work will directly shape our silicon roadmap.

Key Responsibilities

• Own the RISC-V CPU microarchitecture and RTL implementation , including pipeline, ISA extensions, and interfaces.
• Evaluate and compare open-source RISC-V cores (e.g., Rocket, BOOM, CVA6, Ibex, etc.), assessing performance, scalability, and design quality.
• Architect enhancements or new cores tailored to specific application domains and system-level requirements.
• Develop and maintain high-quality, synthesizable RTL in SystemVerilog or Verilog.
• Define verification strategy and collaborate on UVM, formal, or FPGA-based validation of the core.
• Optimize for PPA (Performance, Power, Area) targets through microarchitectural tuning and synthesis feedback.
• Collaborate closely with SoC, memory, and firmware teams to ensure seamless CPU subsystem integration.
• Establish and maintain coding standards, linting, and continuous integration flows for RTL and verification.
• Mentor engineers and help build a small but high-performing front-end design team.

Requirements

• 7+ years of RTL design experience , including at least one CPU or DSP core development project from concept to silicon.
• Deep understanding of CPU microarchitecture , including pipelines, branch prediction, hazards, caches, MMUs, and clock/power domains.
• Strong knowledge of the RISC-V ISA , privilege architecture, and optional extensions.
• Hands-on experience with at least one open-source RISC-V core , such as Rocket, CVA6 (Ariane), Ibex, or BOOM.
• Ability to analyze and improve open-source designs , recognizing their architectural and verification tradeoffs.
• Proficiency in SystemVerilog/Verilog RTL design , simulation, and synthesis.
• Experience with EDA tools (Synopsys, Cadence, or open-source flows) for synthesis and linting.
• Solid understanding of verification methodologies (UVM, formal verification, or constrained-random testing).
• Strong communication and cross-functional collaboration skills.
• Comfort working in a startup environment -hands-on, self-directed, and resourceful.

Preferred Qualifications

• Familiarity with Chisel, SpinalHDL, or TL-Verilog.
• Experience with performance modeling or cycle-accurate simulation frameworks.
• Background in FPGA prototyping or hardware/software co-simulation.
• Contributions to open-source RISC-V or hardware projects.
• Experience leading or mentoring small design teams.

What We Offer

• The opportunity to lead CPU architecture for next-generation RISC-V SoCs.
• A high-impact role with deep technical ownership and creative freedom.
• Collaborative culture with strong engineering focus and minimal bureaucracy.
• Flexible work arrangements and competitive compensation and benefits.

Salary

$225,000 - $300,000 per year