RISC-V RTL Engineer for High-Performance CPU

Tenstorrent; Santa Clara (CA); Hybride; USD 100 000 - 500 000; Plein temps

Résumé du poste

Tenstorrent seeks a talented CPU design engineer to iterate front-end CAD flows for a RISC-V based CPU, collaborating with DV, PD, RTL and performance teams to achieve timing, power, and area convergence. You will perform synthesis, place and route, and work with core micro-architects to optimize configurations for best PPA, while pushing physical design methodologies and tools to improve efficiency.

The role is hybrid, based in Austin or Santa Clara, with learning opportunities across the CPU

Qualifications

• Experience in high-performance physical design.
• Proficient in Verilog/VHDL RTL coding and RTL simulation.
• Experience with synthesis, place and route, and physical design flows.
• Background in CPU micro-architecture.

Responsabilités

• Perform synthesis and initial place and route for new and legacy designs.
• Collaborate closely with core micro-architects to optimize core configurations for best PPA.
• Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
• Enhance physical design environment, tools, and methodologies to improve development efficiency.

Connaissances

RTL coding

Verilog/VHDL

Synthesis & P&R

CPU micro-architecture

Power analysis

Simulation tools

Outils

Synthesis tools

Place & Route tools

Power analysis tools

RTL simulators

Description du poste

Tenstorrent seeks a talented CPU design engineer to iterate front-end CAD flows for a RISC-V based CPU, collaborating with DV, PD, RTL and performance teams to achieve timing, power, and area convergence. You will perform synthesis, place and route, and work with core micro-architects to optimize configurations for best PPA, while pushing physical design methodologies and tools to improve efficiency.

The role is hybrid, based in Austin or Santa Clara, with learning opportunities across the CPU