RISC-V CPU Front-End Physical Lead - RTL & PPA Expert

Tenstorrent; California (MO); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking an engineer to lead the front-end RTL physical implementation for a high‑performance RISC‑V CPU. You will drive CAD flows, define floorplans, and collaborate with microarchitecture, RTL, and PD teams to optimize frequency, power, and area.

This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience and a compensation package reflecting base and variable components.

Qualifications

• Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU
• Work closely with microarchitects and RTL designers to optimize frequency, power, and area across process nodes
• Define initial floorplans and early area, power, and frequency estimates for key CPU and subsystem configurations

Responsibilities

• Lead front‑end physical implementation and PPA definition
• Work closely with microarchitects and RTL designers to optimize frequency, power, and area across process nodes
• Define initial floorplans and early area, power, and frequency estimates
• Partner with PD leads to improve methodologies, flows, and collateral for CPU/IP
• Communicate PPA trade‑offs to RISC‑V and PD teams
• Drive physical design experiments and evaluate results

Skills

Physical design

RTL coding

Place & route

PPA optimization

CPU micro-architecture

Job description

Tenstorrent is seeking an engineer to lead the front-end RTL physical implementation for a high‑performance RISC‑V CPU. You will drive CAD flows, define floorplans, and collaborate with microarchitecture, RTL, and PD teams to optimize frequency, power, and area.

This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience and a compensation package reflecting base and variable components.