Remote Senior ASIC Physical Design Engineer – Signoff Ready

positron.ai; Stati Uniti; Remoto; USD 140.000 - 230.000; Tempo pieno

Vantaggi offerti da questo lavoro

Remote-first work

Company computer

Medical coverage

Dental coverage

Vision coverage

Equity

401(k) match

Unlimited PTO

Descrizione del lavoro

positron.ai is seeking an experienced physical design engineer to own blocks of advanced AI accelerator ASICs from floorplanning to tapeout. You will optimize power, performance, and area while collaborating with RTL, synthesis, DFT, packaging, and backend teams in a remote-first environment.

The role requires hands-on experience with Innovus-based flows and signoff tools, and you will contribute to power-grid methods and hierarchical implementation for complex multi-block chips.

Competenze

• Hands-on ASIC block implementation with Innovus-based flows.
• Familiar with ICC2, Tempus, PrimeTime, Voltus, RedHawk, Calibre.
• Able to close timing, power, area, congestion, DRC/LVS/EM/IR.
• Experience from floorplanning through tapeout.
• Collaborates across RTL, synthesis, DFT, packaging, and backend teams.

Mansioni

• Support floorplanning, macro placement, power planning, and bump planning.
• Run clock tree synthesis, place and route, and routing optimization through timing closure.
• Resolve signoff issues (DRC/LVS/IR/EM) and implement ECOs and metal fill.
• Contribute to power-grid methods, congestion analysis, and hierarchical implementation.
• Coordinate delivery with RTL, synthesis, DFT, package, and backend partners.
• Support physical-design tapeout signoff for owned blocks.

Conoscenze

ASIC physical design

Innovus-based flows

Timing closure

Cross-team collaboration

Power/IR/EM analysis

Strumenti

ICC2

Tempus

PrimeTime

Voltus

RedHawk

Calibre

Descrizione del lavoro

positron.ai is seeking an experienced physical design engineer to own blocks of advanced AI accelerator ASICs from floorplanning to tapeout. You will optimize power, performance, and area while collaborating with RTL, synthesis, DFT, packaging, and backend teams in a remote-first environment.

The role requires hands-on experience with Innovus-based flows and signoff tools, and you will contribute to power-grid methods and hierarchical implementation for complex multi-block chips.