Senior ASIC Physical Design Engineer

eTeam; San Diego (CA); Vor Ort; USD 120.000 - 160.000; Teilzeit

Zusammenfassung

eTeam is seeking a Senior Engineer - Physical Design to contribute to ASIC implementation across floorplanning, power planning, placement and routing, clock tree synthesis, timing closure, and signoff activities. You will collaborate with architecture, RTL, DFT, CAD, and product teams to deliver high-performance, low-power SoCs and IP blocks from synthesis through tapeout.

Candidates should have strong expertise in physical implementation methodologies, scripting, and tool flows using Cadence

Qualifikationen

• Bachelor's degree and 4+ years of ASIC design/verification experience or related work.
• Master's degree and 3+ years of ASIC experience or
• PhD and 2+ years of ASIC design, verification, validation, or related work.

Aufgaben

• Floorplanning and power planning.
• Place and route, clock tree synthesis.
• Timing closure and signoff activities.
• Signal integrity analysis and physical verification.
• ECO implementation and design signoff coordination.

Kenntnisse

Physical design

Timing closure

Low-power design

Automation

Design optimization

Linux/Unix environments

Python

Tcl

Perl

Shell

Analytical skills

Ausbildung

Bachelor's degree in Science/Engineering or related field

Master's degree in Science/Engineering or related field

PhD in Science/Engineering or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

RC extraction

Jobbeschreibung

eTeam is seeking a Senior Engineer - Physical Design to contribute to ASIC implementation across floorplanning, power planning, placement and routing, clock tree synthesis, timing closure, and signoff activities. You will collaborate with architecture, RTL, DFT, CAD, and product teams to deliver high-performance, low-power SoCs and IP blocks from synthesis through tapeout.

Candidates should have strong expertise in physical implementation methodologies, scripting, and tool flows using Cadence