ASIC Physical Design Engineer, Senior

positron.ai; United States; Remote; USD 140,000 - 230,000; Full time

Benefits offered by this job

Remote-first work

Company computer

Medical coverage

Dental coverage

Vision coverage

Equity

401(k) match

Unlimited PTO

Job summary

positron.ai is seeking an experienced physical design engineer to own blocks of advanced AI accelerator ASICs from floorplanning to tapeout. You will optimize power, performance, and area while collaborating with RTL, synthesis, DFT, packaging, and backend teams in a remote-first environment.

The role requires hands-on experience with Innovus-based flows and signoff tools, and you will contribute to power-grid methods and hierarchical implementation for complex multi-block chips.

Qualifications

• Hands-on ASIC block implementation with Innovus-based flows.
• Familiar with ICC2, Tempus, PrimeTime, Voltus, RedHawk, Calibre.
• Able to close timing, power, area, congestion, DRC/LVS/EM/IR.
• Experience from floorplanning through tapeout.
• Collaborates across RTL, synthesis, DFT, packaging, and backend teams.

Responsibilities

• Support floorplanning, macro placement, power planning, and bump planning.
• Run clock tree synthesis, place and route, and routing optimization through timing closure.
• Resolve signoff issues (DRC/LVS/IR/EM) and implement ECOs and metal fill.
• Contribute to power-grid methods, congestion analysis, and hierarchical implementation.
• Coordinate delivery with RTL, synthesis, DFT, package, and backend partners.
• Support physical-design tapeout signoff for owned blocks.

Skills

ASIC physical design

Innovus-based flows

Timing closure

Cross-team collaboration

Power/IR/EM analysis

Tools

ICC2

Tempus

PrimeTime

Voltus

RedHawk

Calibre

Job description

Role overview

Own physical implementation work for assigned blocks of advanced AI accelerator ASICs, helping take designs from early floorplanning through tapeout. The role focuses on achieving signoff-quality power, performance, and area results while contributing to implementation methods for complex, multi-block chips.

Responsibilities

• Support floorplanning, macro placement, power planning, and bump planning.
• Run clock tree synthesis, place and route, and routing optimization through timing closure.
• Resolve signal integrity, IR/EM, congestion, DRC, LVS, and other signoff issues; implement ECOs and metal fill.
• Contribute to power-grid methods, congestion analysis, wire estimation, and hierarchical implementation strategies.
• Coordinate implementation deliverables with RTL, synthesis, DFT, package, and backend design partners.
• Support physical-design tapeout signoff for owned blocks.

Requirements

• Hands-on experience implementing ASIC blocks with Innovus-based flows.
• Practical familiarity with physical-design and signoff tools such as ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre.
• Ability to close designs across timing, power, area, congestion, DRC, LVS, EM, and IR constraints.
• Experience contributing to physical implementation from floorplanning through tapeout.
• Ability to collaborate across design and implementation teams on complex chip work.

Benefits and work setup

• Remote-first work, with a company-provided computer and home-office setup.
• Company-paid medical, dental, vision, life, and disability coverage; additional supplemental coverage is available.
• Unlimited paid time off, 13 paid holidays, competitive salary and equity, and a 401(k) with company match.
• Applicants must already be authorized to work in the U.S.; new visa sponsorship is unavailable, though eligible H-1B transfers may be supported.