Remote ASIC Power Optimization Engineer

positron.ai; USA; Remote; USD 140.000 - 230.000; Vollzeit

Benefits dieser Stelle

Company-provided equipment

Fully paid medical/dental/vision

Life and disability coverage

Supplemental insurance

Unlimited paid time off

13 company holidays

Salary and equity

401(k) matching

Zusammenfassung

Positron.ai is seeking a senior-level power analysis engineer to drive estimation, optimization, and verification for ASIC blocks in an AI accelerator program. You will contribute to chip-level power strategy and advance analysis methods across design lifecycle, from architectural estimates to RTL and gate-level analysis and silicon validation.

Responsibilities include owning power approaches for blocks (dynamic, leakage, clock, memory, interconnect, idle, peak), building models from early

Qualifikationen

• Senior-level experience in physical design power analysis, optimization, or verification for ASICs.
• Ability to model and analyze power across architectural, RTL, and gate-level stages.
• Practical experience with low-power design techniques and activity-based analysis.
• Understanding of power integrity and collaboration with backend implementation teams.
• Clear communication skills for turning analysis into design recommendations.

Aufgaben

• Own power approaches for assigned blocks, covering dynamic and leakage power as well as clock, memory, interconnect, idle, and peak power.
• Build and maintain power models from early design stages through RTL and gate-level implementation.
• Analyze vector-based and activity-driven power data against representative workload behavior.
• Apply optimization methods such as clock gating, operand isolation, power gating, voltage islands, and multi-threshold cells.
• Identify opportunities to reduce memory, pipeline, switching, and data-movement power, and provide actionable feedback to RTL teams.
• Work with backend teams on power integrity, including IR-drop analysis and related implementation concerns.

Kenntnisse

Power analysis

ASIC power optimization

RTL/gate-level analysis

Low-power techniques

Power integrity

Cross-team collaboration

Clear communication

Jobbeschreibung

Positron.ai is seeking a senior-level power analysis engineer to drive estimation, optimization, and verification for ASIC blocks in an AI accelerator program. You will contribute to chip-level power strategy and advance analysis methods across design lifecycle, from architectural estimates to RTL and gate-level analysis and silicon validation.

Responsibilities include owning power approaches for blocks (dynamic, leakage, clock, memory, interconnect, idle, peak), building models from early