Remote RTL Front-End Design Engineer (ASIC/FPGA)

HumanitApp; San Francisco (CA); À distance; USD 96 000 - 165 000; Temps partiel

Avantages offerts par ce poste

Remote work

Projects with leading LLM companies

40 hours per week with PST overlap

Contractor engagement (no medical/paid

2 months duration

Résumé du poste

Turing, based in San Francisco, is seeking a front-end RTL design engineer to craft tasks for AI hardware evaluation. You will turn real RTL work into tasks and reference solutions, covering RTL, bug-fix, and PPA problems for real IP, and ensure they pass rigorous synthesis, timing, and equivalence checks.

You will work on design tasks through commercial and open-source flows, explain area, timing, and power results, and contribute to the ground-truth data used to train AI models.

Qualifications

• BS/MS in Electrical, Electronic, or Computer Engineering or equivalent practical experience.
• 3+ years of front-end digital design on ASIC or FPGA projects.
• Fluent Verilog / SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, clocks, and gating.
• Synthesis and PPA: timing-constrained logic synthesis and reading timing/ROCs.
• Commercial EDA: Cadence Genus, Synopsys Design Compiler / Fusion Compiler, or AMD Vivado.
• Open-source EDA: Yosys, OpenLane/LibreLane, and open-source simulation (Icarus Verilog/Verilator).
• Verification: cocotb or SystemVerilog testbenches; waveform-level debugging.
• Scripting: Python and Tcl; Linux, Git, and Docker-based workflows.

Responsabilités

• Author design tasks: turn real IP into RTL design, bug-fix, and PPA-optimization tasks with spec, starting point, and reference solution.
• Set the PPA bar by running synthesis to establish area, power, and timing baselines and targets.
• Prove correctness with hidden tests and equivalence checks; ensure no design can trade function for a better number.
• Break tasks by attacking for removed logic, constraint gaps, and untested corners.

Connaissances

RTL design

Verilog / SystemVerilog

Python

Tcl

Linux

Git

Cocotb

Icarus Verilog

Verilator

Scripting

Formation

BS/MS in Electrical, Electronic, or Computer Engineering

Outils

Cadence Genus

Synopsys Design Compiler / Fusion Compiler

AMD Vivado

Yosys

OpenLane

LibreLane

Description du poste

Turing, based in San Francisco, is seeking a front-end RTL design engineer to craft tasks for AI hardware evaluation. You will turn real RTL work into tasks and reference solutions, covering RTL, bug-fix, and PPA problems for real IP, and ensure they pass rigorous synthesis, timing, and equivalence checks.

You will work on design tasks through commercial and open-source flows, explain area, timing, and power results, and contribute to the ground-truth data used to train AI models.