Front End Design Engineer

Turing; United States; Remote; USD 96,000 - 165,000; Full time

Benefits offered by this job

Work in a fully remote environment

Cutting-edge AI projects with leadingL

Job summary

Turing is seeking a front-end design engineer to create RTL design tasks for evaluating AI hardware models. You will turn real IP into precise RTL designs, fix bugs, and optimize for PPA across area, power, and timing.

The role emphasizes writing RTL, passing through synthesis, and explaining the resulting area, timing, and power. This is a contractor arrangement with fully remote work, overlapping PST hours.

Qualifications

• BS/MS in Electrical, Electronic, or Computer Engineering or equivalent practical experience.
• 3+ years of front-end digital design on ASIC/FPGA projects, RTL through synthesis.
• Fluent Verilog / SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, FIFOs, clock-domain crossings, clock gating.

Responsibilities

• Author design tasks: turn real IP into precise RTL design, bug-fix, and PPA tasks with a reference solution.

Skills

RTL design

Verilog/SystemVerilog

Python

Linux

Git & Docker

Education

BS/MS in Electrical, Electronic, or Computer Engineering

Tools

Cadence Genus

Synopsys Design Compiler / Fusion Compiler

AMD Vivado (Vitis HLS)

Yosys

Icarus Verilog

Verilator

Job description

Create RTL design tasks for evaluating AI hardware design models.

About Turing

Based in San Francisco, California, Turing is the world’s leading research accelerator for frontier AI labs and a trusted partner for global enterprises deploying advanced AI systems. Turing supports customers in two ways: first, by accelerating frontier research with high-quality data, advanced training pipelines, plus top AI researchers who specialize in coding, reasoning, STEM, multilinguality, multimodality, and agents; and second, by applying that expertise to help enterprises transform AI from proof of concept into proprietary intelligence with systems that perform reliably, deliver measurable impact, and drive lasting results on the P&L

Role Overview

We build hardware-engineering training data and benchmarks for frontier AI labs. As a front-end design engineer, you turn real RTL work into tasks that measure how well AI models design hardware: each task has a specification, a starting design, a reference solution, and the tests that grade it.In this track, you will build the design tasks themselves: RTL design, bugfix, and PPA (power, performance, area) problems on real IP, graded with the same simulation, synthesis, and equivalence-checking flows used to tape out chips. This is fundamentally a front-end design role: you write RTL, take it through commercial and open-source synthesis, and can explain why the area, timing, and power came out the way they did.The artifacts you produce become the ground truth these models learn from and are measured against. Your specifications, reference solutions, and tests shape what the next generation of models learns about digital design, so each one must hold up to the same scrutiny as a design going to tape-out.

What does day-to-day life look like?

• Author design tasks: Turn real IP into precise RTL design, bug-fix, and PPA‑optimization tasks: the specification, the starting point, and a reference solution that meets every requirement.
• Set the PPA bar: Run commercial and open-source synthesis to establish area, power, and timing baselines, and set targets that reward real engineering rather than lucky tool settings.
• Prove correctness: Build the hidden tests and equivalence checks a solution must pass, so no design can trade away function for a better number.
• Break your own tasks: Attack each task the way a model would (removed logic, constraint loopholes, untested corners) and close the gaps before it ships.

Requirements

• Education: BS/MS in Electrical, Electronic, or Computer Engineering, or equivalent practical experience.
• Experience: 3+ years of front-end digital design on ASIC or FPGA projects, from RTL through synthesis.
• RTL design: Fluent Verilog / SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, FIFOs, clock-domain crossings, and clock gating.
• Synthesis and PPA: Hands-on logic synthesis with timing constraints. You read timing and quality-of-results reports and know which RTL or constraint change moves area, timing, or power.
• Commercial EDA: Hands-on commercial synthesis in industry, research, or project work: Cadence Genus, Synopsys Design Compiler / Fusion Compiler, or, for FPGA targets, AMD Vivado (including Vitis HLS flows).
• Open-source EDA: Hands-on open-source synthesis with Yosys, directly or through an OpenLane / LibreLane flow, and open-source simulation with Icarus Verilog or Verilator, directly or under cocotb.
• Verification: Self-checking testbenches in cocotb (Python) or SystemVerilog, and waveform-level debug.
• Scripting: Python and Tcl for flow automation; at home in Linux, Git, and Docker‑based environments. This is how every task runs.

Perks of Freelancing With Turing

• Work in a fully remote environment.
• Opportunity to work on cutting-edge AI projects with leading LLM companies.

Offer Details

• Commitments Required:Minimum 40 hours per week with daily overlap of 4 hours with PST.
• Engagement Type: Contractor assignment (no medical/paid leave)
• Duration of Contract:2 months (adjustable based on engagement)
• Location:

Evaluation Process

• Technical Interview

Skills:

Python