Senior Verification Architect for High-Performance IP/SoC

Credo; Pittsburgh (Allegheny County); On-site; USD 92,000 - 154,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Job summary

Credo seeks a hands-on verification engineer to contribute to digital design verification for high-performance networking IP. You will architect scalable UVM testbenches, support UVM development, and align with design and architecture teams to deliver silicon.

You will lead regression planning, coverage, and verification sign-off while collaborating across design, firmware, emulation, and post-silicon teams to ensure robust verification of complex data-path designs.

Qualifications

• Seven or more years of relevant experience in ASIC/SoC verification.
• Leadership in verification methodology and execution.
• Strong understanding of digital design concepts including state machines, data paths, FIFOs, clock-domain crossings, resets, low-power behavior, and performance-sensitive architectures.
• Expertise in SystemVerilog, UVM, constrained-random verification, assertion-based verification, and development of synthesizable and behavioral models where appropriate with emphasis on configurability and reuse.
• Strong automation and scripting skills in Python, Perl, Tcl, and shell for regressions, reporting, stimulus, and workflow optimization.
• Advanced debugging skills across RTL, testbench, waveforms, assertions, and regression failures.
• Networking protocols, specifically 802.3 (Ethernet), PCIe, CXL, and related standards.
• On-chip bus and interconnect protocols including AMBA: CHI, AXI, APB, etc.
• Forward Error Correction (FEC) algorithms.
• Experience with Cadence, Mentor, and Synopsys tool suites for simulation, lint, and synthesis.
• Knowledge of AI workloads is a plus.

Responsibilities

• Define end-to-end verification strategy and architect reusable, scalable UVM-based testbench frameworks for IP and subsystem-level verification.
• Translate architecture and functional specifications into verification plans, test scenarios, checkers, assertions, and coverage models.
• Lead the development of reusable UVM verification components including agents, drivers, monitors, scoreboards, reference models, and constrained-random stimulus.
• Own regression planning and execution, failure triage, debug, root-cause analysis, and verification sign-off criteria.
• Drive functional and code coverage closure, identify verification gaps, and improve methodology for quality and efficiency.
• Partner with design, architecture, firmware, emulation, and post-silicon teams to ensure robust verification of complex data-path and protocol-centric designs.
• Review microarchitecture for testability and observability, and influence design decisions that improve verification effectiveness and debug productivity.
• Develop automation and scripting infrastructure to improve regressions, reporting, stimulus generation, and verification productivity.
• Lead design and verification reviews, establish best practices, and mentor engineers on methodology, coding quality, and debug techniques.
• Support critical product and field issues requiring deep insight into architecture, RTL behavior, and verification environment behavior.
• Ensure compliance with relevant standards, as well as internal and external specifications.
• Evaluate AI-driven verification techniques and streamline existing methodologies around AI-enhanced solutions.

Skills

ASIC/SoC verification

Digital design concepts

SystemVerilog/UVM/CRV/Assertions

Python/Perl/Tcl/Shell scripting

RTL/testbench/debug

Networking protocols (Ethernet PCIe CX

AMBA CHI/AXI/APB

FEC algorithms

AI workloads

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence

Mentor

Synopsys

Job description

Credo seeks a hands-on verification engineer to contribute to digital design verification for high-performance networking IP. You will architect scalable UVM testbenches, support UVM development, and align with design and architecture teams to deliver silicon.

You will lead regression planning, coverage, and verification sign-off while collaborating across design, firmware, emulation, and post-silicon teams to ensure robust verification of complex data-path designs.