Design Verification Engineer – IP

HCL Technologies Limited; California; Remote; USD 95,000 - 192,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Life insurance

401(k) retirement plan

Paid time off

Job summary

HCLTech is seeking a highly talented Design Verification Engineer - IP to advance innovation through IP verification and reusable verification environments. The role emphasizes SystemVerilog, UVM, RAL modeling, and thorough coverage closure.

The candidate will implement verification plans, directed and constrained-random tests, and collaborate with RTL and SoC teams to deliver high-quality collateral and sign-off readiness.

Qualifications

• Strong experience with SystemVerilog and UVM.
• Hands-on IP verification and verification environment development.
• Understanding of digital design fundamentals, RTL, FSMs, and verification methodologies.

Responsibilities

• Develop reusable SystemVerilog/UVM-based verification environments including testbenches, agents, monitors, drivers, scoreboards, sequences, and assertions.
• Develop and execute verification plans, test cases, and functional coverage models.
• Create directed and constrained-random test scenarios for IP/block-level verification.
• Integrate and debug UVCs/VIPs within the verification environment.
• Drive functional and code coverage closure and analyze coverage gaps.
• Verify RTL functionality of IP blocks including FSMs and control logic.
• Perform RAL-based register verification including access, prediction, mirroring and coverage.
• Debug RTL, protocol, testbench and verification environment issues.
• Perform regression analysis and support verification sign-off.
• Support low-power verification and GLS debugging as required.
• Collaborate with RTL design and SoC teams to deliver reusable verification collateral.

Skills

SystemVerilog

UVM

IP Verification

RTL

RAL modeling

Assertions

Coverage-driven verification

GLS debugging

Regression analysis

Debugging

Tools

UVCs/VIPs

Job description

HCLTech is looking for a highly talented and self-motivated Design Verification Engineer - IP to join it in advancing the technological world through innovation and creativity.

Job ID: 153898

Position Type: Full Time

Location: Remote

We are looking for an experienced Design Verification Engineer responsible for IP verification, including development of reusable verification environments, execution of verification plans, RTL debugging, regression analysis, and functional/code coverage closure.

The ideal candidate will have strong hands‑on experience with SystemVerilog, UVM, RAL modeling, assertions, coverage-driven verification, and RTL/IP verification.

Key Responsibilities

• Develop and enhance reusable SystemVerilog/UVM-based verification environments, including testbenches, agents, monitors, drivers, scoreboards, sequences, and assertions.
• Develop and execute comprehensive verification plans, test cases, and functional coverage models.
• Create and execute directed and constrained-random test scenarios for IP/Block-level verification.
• Integrate, configure, and debug UVCs/VIPs within the verification environment.
• Drive functional coverage and code coverage closure, including identification and analysis of coverage gaps.
• Verify RTL functionality of IP blocks, including FSMs, DAC control logic, and pattern memory/controller modules.
• Perform RAL modeling and RAL-based register verification, including register access, prediction, mirroring, and coverage.
• Debug RTL, protocol, testbench, simulation, and verification environment issues.
• Perform regression analysis and support verification sign-off activities.
• Support low‑power verification and Gate-Level Simulation (GLS) debugging as required.
• Collaborate closely with RTL design and SoC teams to deliver high‑quality, reusable verification environments and collateral.

Required Skills

• Strong programming experience in SystemVerilog and UVM.
• Hands‑on experience with IP Verification and verification environment development.
• Strong understanding of digital design fundamentals, RTL, FSM architectures, and verification methodologies.
• Strong hands‑on experience with UVM RAL / Register Abstraction Layer modeling and verification.
• Experience with register access, prediction, mirroring, register coverage, and RAL-based verification sequences.
• Experience with directed testing and constrained‑random verification.
• Experience with functional coverage, code coverage, assertions, and coverage closure.
• Experience integrating and debugging UVCs/VIPs.
• Strong experience with RTL and protocol debugging.
• Experience with regression execution, failure analysis, and debugging.
• Familiarity with low‑power verification concepts and GLS debug.
• Strong analytical, debugging, and problem‑solving skills.
• Ability to work effectively with Design, Verification, and SoC engineering teams.

Pay and Benefits

Pay Range Minimum: $95000/Year

Pay Range Maximum: $192000/Year

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to [e-mail] for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year

How You’ll Grow

At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior‑level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.