Design Verification Engineer

Mumba Technologies, Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Mumba Technologies, Inc. seeks a Design Verification Engineer to join our Interface IP DV team.

You will work with architects, designers, and vendors to ensure architecture requirements are met in IP subsystems and interfaces, validating correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges while collaborating with RTL, software, and emulation teams to drive robust,

Qualifications

• 8+ years of design verification experience.
• Hands-on experience with SystemVerilog/UVM and scalable testbenches.
• Comfortable with IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

Responsibilities

• End to end ownership of one or more IP subsystems (PCIe, Ethernet, CPU, low power peripherals, sensors).
• Understand vendor IP configurations and coordinate with internal IP team.
• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness and performance.
• Collaborate with integration and SoC DV teams to validate interaction of external IPs within the chip architecture.
• Drive coverage closure and sign-off by defining metrics and analyzing gaps.

Skills

8+ years DV experience

SystemVerilog/UVM

IP interfaces PCIe Ethernet AXI/AMBA

Startup collaboration

Tools

SystemVerilog

UVM

Testbenches

Job description

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

• End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
• Understand vendor IP configurations and handle handshake with internal IP team
• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

• 8+ years of design verification experience
• You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
• You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
• You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
• You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
• You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

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