Ethernet IP Verification Engineer - SystemVerilog/UVM

Talent 101, Inc; Dallas (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Talent 101 seeks an experienced Ethernet IP Design Verification Engineer for a contract semiconductor engagement in Dallas, TX. The engineer will verify Ethernet IP, develop verification plans, build testbenches, and drive regression and coverage across interfaces and modes.

The ideal candidate has Ethernet/IP DV experience, strong SystemVerilog/UVM skills, and a proven ability to debug RTL/testbench interactions, develop checkers, and ensure verification closure with robust coverage.

Qualifications

• Strong ASIC or semiconductor design verification experience.
• Hands-on verification experience with Ethernet or networking IP.
• Strong SystemVerilog and UVM experience.
• Experience developing verification plans and testcase strategies from specifications.
• Experience building or modifying UVM testbenches, sequences, drivers, monitors, scoreboards, and coverage models.
• Strong constrained-random verification and functional coverage experience.
• Strong regression debugging and waveform-analysis skills.
• Understanding of Ethernet frames, packet processing, protocol behavior, and networking concepts.
• Ability to debug interactions between RTL and verification environments.
• Experience working closely with RTL designers, architects, and other verification engineers.

Responsibilities

• Develop and execute verification plans for Ethernet and networking IP blocks.
• Build, enhance, and maintain SystemVerilog/UVM verification environments.
• Develop directed and constrained-random testcases for networking functionality.
• Generate and verify Ethernet packet traffic across supported interfaces and operating modes.
• Develop checkers, scoreboards, monitors, assertions, functional coverage, and verification components.
• Verify protocol behavior, packet handling, configuration, control/status paths, error handling, and corner cases.
• Run regressions, analyze failures, debug waveforms, and identify root causes in RTL, testbench, or verification infrastructure.
• Work closely with RTL designers and architects to clarify requirements and resolve design issues.
• Measure functional and code coverage and drive verification closure.
• Reuse and modify existing verification IP and testbench components where appropriate.
• Support IP-level and, when required, subsystem/SoC-level integration verification.
• Document verification results, open issues, coverage status, and test completion.

Skills

SystemVerilog

UVM

Verification planning

Constrained-random testing

Debug waveform analysis

Ethernet/IP DV

Testbench development

Regression debugging

Job description

Talent 101 seeks an experienced Ethernet IP Design Verification Engineer for a contract semiconductor engagement in Dallas, TX. The engineer will verify Ethernet IP, develop verification plans, build testbenches, and drive regression and coverage across interfaces and modes.

The ideal candidate has Ethernet/IP DV experience, strong SystemVerilog/UVM skills, and a proven ability to debug RTL/testbench interactions, develop checkers, and ensure verification closure with robust coverage.