Principal Silicon Validation Engineer - Post-Silicon

Ayar Labs, Inc.; San Jose (CA); On-site; USD 200,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Stock options

Job summary

Ayar Labs, Inc. is seeking a Principal Engineer, Silicon Validation in San Jose to lead the validation of optical chiplets and drive signoff from power-on to system level. You will shape test plans, bring-up conditions, and post-silicon validation for SerDes interfaces and mixed-signal blocks.

You will collaborate with firmware and design teams, applying industry standards and best practices to ensure robust performance. Strong Python, leadership, and communication are essential.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
• Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
• Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
• Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
• Experience developing and owning validation test plans end-to-end.
• Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
• Excellent communication skills and ability to drive cross-functional technical alignment.

Responsibilities

• Lead Validation Strategy: Define and implement comprehensive validation methodologies for electronic-photonic SoCs, covering bringup, functional validation, electrical characterization, and system-level testing.
• Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs with firmware and design teams.
• Own Block and System Validation: Perform post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks.
• Apply Standards and Best Practices: Use IEEE, OIF, JEDEC, Ethernet/Optical MSA specs to set targets and signoff criteria.
• Root Cause and Debug: Investigate silicon failure modes and drive to closure with cross-functional teams.
• Mentor and Lead: Provide technical leadership and mentorship to validation engineers.
• Deliver High Quality Documentation: Create validation reports, signoff packages, and product performance docs.

Skills

Leadership

Python

SerDes validation

Lab automation

Test planning

Communication

Education

Bachelor's degree in Electrical Engineering

Master's degree in EE

Tools

BERT

Oscilloscopes

VNA

DCA

Network analyzers

Job description

Ayar Labs, Inc. is seeking a Principal Engineer, Silicon Validation in San Jose to lead the validation of optical chiplets and drive signoff from power-on to system level. You will shape test plans, bring-up conditions, and post-silicon validation for SerDes interfaces and mixed-signal blocks.

You will collaborate with firmware and design teams, applying industry standards and best practices to ensure robust performance. Strong Python, leadership, and communication are essential.