Principal Engineer, Post-silicon Validation

Ayar Labs, Inc.; San Jose (CA); On-site; USD 200,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Stock options

Job summary

Ayar Labs, Inc. is seeking a Principal Engineer, Silicon Validation in San Jose to lead the validation of optical chiplets and drive signoff from power-on to system level. You will shape test plans, bring-up conditions, and post-silicon validation for SerDes interfaces and mixed-signal blocks.

You will collaborate with firmware and design teams, applying industry standards and best practices to ensure robust performance. Strong Python, leadership, and communication are essential.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
• Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
• Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
• Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
• Experience developing and owning validation test plans end-to-end.
• Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
• Excellent communication skills and ability to drive cross-functional technical alignment.

Responsibilities

• Lead Validation Strategy: Define and implement comprehensive validation methodologies for electronic-photonic SoCs, covering bringup, functional validation, electrical characterization, and system-level testing.
• Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs with firmware and design teams.
• Own Block and System Validation: Perform post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks.
• Apply Standards and Best Practices: Use IEEE, OIF, JEDEC, Ethernet/Optical MSA specs to set targets and signoff criteria.
• Root Cause and Debug: Investigate silicon failure modes and drive to closure with cross-functional teams.
• Mentor and Lead: Provide technical leadership and mentorship to validation engineers.
• Deliver High Quality Documentation: Create validation reports, signoff packages, and product performance docs.

Skills

Leadership

Python

SerDes validation

Lab automation

Test planning

Communication

Education

Bachelor's degree in Electrical Engineering

Master's degree in EE

Tools

BERT

Oscilloscopes

VNA

DCA

Network analyzers

Job description

Principal Engineer, Silicon Validation

Location: San Jose (on-site)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

In this role, you will lead the silicon validation of our optical chiplets. You will define and drive the validation strategy from initial silicon power-on through block and chip level signoff. This is a rare opportunity to apply deep expertise in high-speed SerDes, photonic systems, and post-silicon validation to shape the future of optical interconnect for next-generation AI infrastructure.

Essential Functions

• Lead Validation Strategy: Define and implement comprehensive validation methodologies for our electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing. Develop detailed test plans, success criteria, and select appropriate test equipment and methodologies.
• Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality from day one.
• Own Block and System Validation: Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using industry-standard lab equipment (BERT, DCA, oscilloscopes, OSA, VNA).
• Apply Standards and Best Practices: Draw on industry standards (IEEE, OIF, JEDEC, Ethernet/Optical MSA specs) and semiconductor validation best practices to establish rigorous validation targets, coverage objectives, and signoff criteria.
• Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
• Mentor and Lead: Provide technical leadership and mentorship to senior and junior validation engineers; guide the team's technical execution.
• Deliver High Quality Documentation: Create and maintain comprehensive validation reports, signoff packages, and product performance documentation.

Required Qualifications

• Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
• Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
• Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
• Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
• Experience developing and owning validation test plans end-to-end.
• Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
• Excellent communication skills and ability to drive cross-functional technical alignment.

Preferred Qualifications

• MSEE or equivalent
• Familiarity with optical transceiver standards and co-packaged optics integration challenges.
• Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, OIF CEI.
• Experience driving NPI and transition from lab validation to manufacturing test.

Salary Range: $200,000 - $255,000

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.