Principal Post-Silicon Validation Engineer: AI Connectivity

Astera Labs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs in San Jose, CA is seeking a Principal Post-Silicon Validation Engineer to lead the validation strategy for high-speed interconnect products. You will drive lab bring-up, characterize silicon, and perform root-cause analysis, influencing production readiness and time-to-market for AI infrastructure solutions.

Responsibilities include designing test plans, enabling automation with Python and C/C++, mentoring engineers, and collaborating with design and product teams to ensure robust

Qualifications

• Required: Bachelor's degree in Electrical or Computer Engineering or related field.
• 8–12 years of hands-on post-silicon validation or hardware characterization.
• Proficiency with PCIe physical layer and high-speed serial interfaces.
• Strong scripting in Python and/or C/C++ for test automation.
• Proven debugging of complex hardware/firmware issues to root cause.

Responsibilities

• Architect and drive post-silicon validation plans from bring-up to production release.
• Define tests, coverage goals and exit criteria with design and product teams.
• Lead lab bring-up of new silicon including board, firmware, and software readiness.
• Mentor engineers and set validation best practices across the team.
• Collaborate with customers and Field Applications Engineers to resolve issues.

Skills

8-12 years experience in post-silicon

PCIe high-speed interfaces

Python/C/C++ for test automation

Hardware/firmware debugging

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree or PhD in Electrical Engineering or Computer Engineering

Tools

Oscilloscopes

BERTs

Protocol analyzers

Power supplies

Job description

Astera Labs in San Jose, CA is seeking a Principal Post-Silicon Validation Engineer to lead the validation strategy for high-speed interconnect products. You will drive lab bring-up, characterize silicon, and perform root-cause analysis, influencing production readiness and time-to-market for AI infrastructure solutions.

Responsibilities include designing test plans, enabling automation with Python and C/C++, mentoring engineers, and collaborating with design and product teams to ensure robust