Senior Silicon Validation Engineer - High-Speed SerDes

InvestedintheMission; San Jose (CA); On-site; USD 200,000 - 255,000; Full time

Job summary

Ayar Labs is seeking a Principal Engineer, Silicon Validation in San Jose. You will lead the validation strategy for electronic-photonic SoCs, drive first silicon bring-up, and oversee post-silicon validation of SerDes interfaces and mixed-signal blocks.

You will mentor engineers and produce comprehensive signoff documentation. Applicants should have a strong background in high-speed SerDes validation, lab automation with Python, and familiarity with Ethernet/PCIe standards.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 10+ years of experience, or Master's with 7+ years.
• Proven leadership in post-silicon validation for complex SoCs or multi-chip packages.
• Hands-on high-speed SerDes validation (NRZ and PAM-4) with BERTs, scopes, and network analyzers.
• Python proficiency for lab automation, data analysis, and test infrastructure.
• Experience developing and owning validation test plans end-to-end and cross-functional alignment.

Responsibilities

• Define and implement comprehensive validation methodologies for electronic-photonic SoCs.
• Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams.
• Execute post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks.
• Apply industry standards and establish signoff targets, coverage objectives and validation plans.
• Investigate and debug silicon failures; collaborate with design and firmware to drive closures.
• Provide technical leadership and mentorship to senior and junior validation engineers.
• Create and maintain validation reports, signoff packages, and product performance documentation.

Skills

Leadership

Post-silicon validation

Python programming

Test planning

Cross-functional communication

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree

Tools

BERTs

Oscilloscopes

DCAs

Network analyzers

VNA

Job description

Ayar Labs is seeking a Principal Engineer, Silicon Validation in San Jose. You will lead the validation strategy for electronic-photonic SoCs, drive first silicon bring-up, and oversee post-silicon validation of SerDes interfaces and mixed-signal blocks.

You will mentor engineers and produce comprehensive signoff documentation. Applicants should have a strong background in high-speed SerDes validation, lab automation with Python, and familiarity with Ethernet/PCIe standards.