Principal Digital Verification & Emulation Architect

Ayar Labs, Inc.; San Jose (CA); On-site; USD 190,000 - 250,000; Full time

Job summary

Ayar Labs, Inc. in San Jose, CA, is seeking a Principal Engineer, Digital Verification & Emulation to lead verification and hardware-assisted validation for our next-generation silicon photonic chip.

You will focus on digital verification, emulation bring-up, mixed-signal-aware verification, real-number modeling, and pre-silicon validation. This senior individual-contributor role collaborates with architecture, RTL design, firmware, software, systems, and validation teams to define verification

Qualifications

• 12+ years of ASIC/SoC verification experience.
• 6+ years hands-on with hardware emulation/acceleration platforms.
• 12+ years digital verification across IP/SoC designs; SystemVerilog; UVM familiarity.
• Strong automation skills using Python, Tcl, Perl, Shell, Make; regression and tooling.

Responsibilities

• Lead hardware-assisted verification using emulation platforms.
• Own emulator bring-up, compile/debug flows, model mapping, and regression execution.
• Build reusable verification environments for IP blocks, subsystems, and SoC-level designs.
• Adapt simulation environments for emulation/acceleration; migrate tests to emulation.
• Develop real-number and mixed-signal models for analog/digital verification.
• Collaborate with firmware/software teams on pre-silicon workloads and diagnostics.
• Define verification plans, testability improvements, and signoff criteria.
• Debug failures across RTL, emulation models, firmware, and mixed-signal blocks.
• Develop automation for regressions, emulation builds, and dashboards.
• Mentor engineers and drive verification methodology.

Skills

SystemVerilog

Python

C/C++

UVM

Verification planning

Debugging

Education

BS in Electrical/Computer Engineering or related field

Tools

Synopsys ZeBu

Cadence Palladium

Siemens Veloce

Job description

Ayar Labs, Inc. in San Jose, CA, is seeking a Principal Engineer, Digital Verification & Emulation to lead verification and hardware-assisted validation for our next-generation silicon photonic chip.

You will focus on digital verification, emulation bring-up, mixed-signal-aware verification, real-number modeling, and pre-silicon validation. This senior individual-contributor role collaborates with architecture, RTL design, firmware, software, systems, and validation teams to define verification