Principal RTL Lead: Architect 400G/800G Ethernet ASIC

MosChip®; Santa Clara (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

A semiconductor design company is seeking a Principal RTL Lead to drive the development of next-generation Ethernet subsystems. This role involves defining architecture for ultra-fast data centers and leading a team in implementing high-speed Ethernet IP. Candidates must have over 10 years of experience in RTL design and a strong background in Ethernet protocols. The position offers a contract duration of 6+ months in the Bay Area, California, with a work week from Monday to Friday.

Qualifications

• 10+ years of experience in RTL design with 3-4 successful tape-outs in advanced process nodes.
• Deep experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers.
• Expert knowledge of full front-end ASIC flow from architectural spec to post-silicon bring-up.

Responsibilities

• Act as the primary architect for the Ethernet subsystem and define micro-architecture.
• Own the implementation of IEEE 802.3 standards and manage massive bus widths.
• Lead the integration of third-party SerDes IP and ensure seamless interoperability.

Skills

RTL design

Ethernet protocols

SystemVerilog

Python

Job description

A semiconductor design company is seeking a Principal RTL Lead to drive the development of next-generation Ethernet subsystems. This role involves defining architecture for ultra-fast data centers and leading a team in implementing high-speed Ethernet IP. Candidates must have over 10 years of experience in RTL design and a strong background in Ethernet protocols. The position offers a contract duration of 6+ months in the Bay Area, California, with a work week from Monday to Friday.