Senior RTL Networking ASIC Engineer: QoS & Latency

Eridu Corporation; Saratoga (CA); On-site; USD 210,000 - 275,000; Full time

Job summary

Eridu Corporation, a Silicon Valley hardware startup, seeks seasoned RTL designers to shape and implement Networking ASICs. You will specify, architect, and productize high‑speed chips for Ethernet/IP interconnects, focusing on latency and QoS.

Join a world‑class engineering team advancing AI data centers and hardware infrastructure. We offer a competitive base salary for SF Bay Area, with a pay range of 210,000–275,000 USD per year, aligned to skills and market trends.

Qualifications

• ME/BE with 8–15 years of experience.
• Hands-on knowledge of SystemVerilog and Verilog.
• Solid understanding of ASIC design methodologies: simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms.
• Experience with Ethernet and IP protocols.
• Strong analytical and problem‑solving skills with meticulous attention to detail in troubleshooting complex networking issues.
• Excellent verbal and written communication skills, and the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Responsibilities

• Packet buffering, queuing, and scheduling: Design microarchitecture and implementation of high‑speed networking ASICs, focusing on latency optimization and QoS support.
• Implementation and Testing: Implement designs on ASIC platforms and ensure compliance with industry standards and performance benchmarks.
• Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support: Provide support for Ethernet, IP protocols, and high‑speed interconnects such as UCIe.
• Troubleshooting and Debugging: Investigate and resolve complex packet‑queuing issues alongside system architects, hardware engineers, and firmware developers.

Job description

Eridu Corporation, a Silicon Valley hardware startup, seeks seasoned RTL designers to shape and implement Networking ASICs. You will specify, architect, and productize high‑speed chips for Ethernet/IP interconnects, focusing on latency and QoS.

Join a world‑class engineering team advancing AI data centers and hardware infrastructure. We offer a competitive base salary for SF Bay Area, with a pay range of 210,000–275,000 USD per year, aligned to skills and market trends.