Lead RTL Architect - 400G/800G Ethernet ASIC

MosChip Technologies Limited; Santa Clara (CA); Presencial; USD 190.000 - 320.000; Jornada completa

Descripción de la vacante

MosChip Technologies Limited in Santa Clara, CA seeks a Principal RTL Lead for High Speed Ethernet ASICs. You will spearhead the Ethernet subsystem architecture for 400G/800G and guide a team of designers through multi-lane, FEC, and clocking challenges.

This role blends deep technical execution with strategic mentoring for rapid silicon delivery. You will own front-end flows from spec to synthesis and formal verification, partnering with FE teams to tackle timing, CDC, and power optimization to

Formación

• 10+ years of RTL design experience in advanced process nodes.
• 3–4 successful tape-outs in leading-edge nodes (7nm/5nm/3nm).
• Strong HDL proficiency, with SystemVerilog and verification basics.
• Deep Ethernet IP knowledge (MAC/PCS/PMA) and 100G/400G/800G stacks.
• Proven leadership and mentorship of design teams.

Responsabilidades

• Technical leadership as the primary architect for the Ethernet subsystem.
• Own IEEE 802.3 protocol implementations including RS-FEC and AN/LT.
• Design high-speed logic, manage wide buses, ensure timing closure.
• Lead FE integration with SerDes IP and MAC/PMA interfaces.
• Drive best practices in verification, lint, and post-silicon bring-up.

Conocimientos

RTL design

SystemVerilog

IEEE 802.3 Ethernet

100G/400G/800G Ethernet

Timing closure

Python/Perl scripting

Tape-out experience

Front-end ASIC flow

Herramientas

Verilog/SystemVerilog

Descripción del empleo

MosChip Technologies Limited in Santa Clara, CA seeks a Principal RTL Lead for High Speed Ethernet ASICs. You will spearhead the Ethernet subsystem architecture for 400G/800G and guide a team of designers through multi-lane, FEC, and clocking challenges.

This role blends deep technical execution with strategic mentoring for rapid silicon delivery. You will own front-end flows from spec to synthesis and formal verification, partnering with FE teams to tackle timing, CDC, and power optimization to