Principal RTL Lead – High Speed Ethernet (ASIC)

MosChip Technologies Limited; Santa Clara (CA); On-site; USD 190,000 - 320,000; Full time

Job summary

MosChip Technologies Limited in Santa Clara, CA seeks a Principal RTL Lead for High Speed Ethernet ASICs. You will spearhead the Ethernet subsystem architecture for 400G/800G and guide a team of designers through multi-lane, FEC, and clocking challenges.

This role blends deep technical execution with strategic mentoring for rapid silicon delivery. You will own front-end flows from spec to synthesis and formal verification, partnering with FE teams to tackle timing, CDC, and power optimization to

Qualifications

• 10+ years of RTL design experience in advanced process nodes.
• 3–4 successful tape-outs in leading-edge nodes (7nm/5nm/3nm).
• Strong HDL proficiency, with SystemVerilog and verification basics.
• Deep Ethernet IP knowledge (MAC/PCS/PMA) and 100G/400G/800G stacks.
• Proven leadership and mentorship of design teams.

Responsibilities

• Technical leadership as the primary architect for the Ethernet subsystem.
• Own IEEE 802.3 protocol implementations including RS-FEC and AN/LT.
• Design high-speed logic, manage wide buses, ensure timing closure.
• Lead FE integration with SerDes IP and MAC/PMA interfaces.
• Drive best practices in verification, lint, and post-silicon bring-up.

Skills

RTL design

SystemVerilog

IEEE 802.3 Ethernet

100G/400G/800G Ethernet

Timing closure

Python/Perl scripting

Tape-out experience

Front-end ASIC flow

Tools

Verilog/SystemVerilog

Job description

Principal RTL Lead – High Speed Ethernet (ASIC)

10+ Years

Full-Time

Principal RTL Lead – High Speed Ethernet (ASIC)

Company Overview :

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

We are seeking a seasoned Principal RTL Lead to spearhead the development of next-generation Ethernet subsystems. This isn't just about moving packets; it's about defining the architecture for 400G, 800G, and beyond. As the technical lead, you will own the logic that powers the world's fastest data centers, ensuring ultra-low latency and rock-solid reliability at massive scale.

Candidate will lead a high-caliber team of designers to implement high-speed Ethernet IP (MAC/PCS/PMA) into our custom ASIC silicon. Your role is a blend of deep technical execution and strategic mentorship—steering the team through the complexities of multi-lane alignment, Forward Error Correction (FEC), and high-speed clocking challenges.

Key Responsibilities

• Technical Leadership: Act as the primary architect for the Ethernet subsystem. You'll define micro-architecture for high-bandwidth data paths and complex control logic.
• Protocol Mastery: Own the implementation of IEEE 802.3 standards, including RS-FEC (254, 256) , multi-lane distribution (MLD), and auto-negotiation/link training (AN/LT).
• High-Speed Logic Design: Solve the "hard problems"ofnetworking: managing massive bus widths (eg, 1024-bit+), minimizing logic depth fortiming closure, and handling complex CDC across asynchronous boundaries.
• Front-End Integration: Lead the integration of third-party SerDes IP and ensure seamless interoperability between the electrical physical layer and the digital MAC.
• Design for Excellence: Drive best practices in coding (SystemVerilog), power optimization (UPF), and lint/CDC/RDC analysis to ensure first-pass silicon success.
• The Track Record: 10+ years of experience in RTL design with at least 3-4 successful tape-outs in advanced process nodes (7nm, 5nm, or 3nm).
• Ethernet Expertise: Deep, hands-on experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers (MAC, PCS, FEC).
• ASIC Lifecycle: Expert knowledge of the full front-end ASIC flow—from architectural spec to synthesis, formal verification, and post-silicon bring-up.
• High-Speed Design: Proven ability to close timing on high-frequency designs () and manage complex clocking architectures.
• Scripting Power: Proficiency in Python or Perl for creating sophisticated design-generation and analysis tools.
• Experience with IEEE 1588 (PTP) hardware stamping for precision timing.
• Familiarity with CXL or PCIe Gen 5/6 protocols.
• Direct experience working with physical design teams on timing and congestion mitigation.