Lead RTL/SoC Design Engineer

TetraMem INC; Fremont (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Competitive compensation

Medical benefits

401k plan

Professional PTO

Job summary

TetraMem INC in Fremont is seeking a Lead RTL Designer to spearhead design, simulation, and verification for our innovative ASIC/SoC products. The role demands a deep understanding of digital design methodologies and the ability to mentor junior engineers.

Ideal candidates will possess a master's or PhD with at least 5 years of experience, along with proficiency in Verilog and System Verilog. We offer a competitive compensation package and excellent benefits.

Qualifications

• 5+ years of experience or PhD with a focus on RTL/SoC/digital design.
• Experience with both pre-layout and post-layout simulation.
• Ability to create innovative architecture to meet customer needs.

Responsibilities

• Lead RTL design, simulation, and verification for TetraMem products.
• Integrate and validate IP blocks, ensuring functionality.
• Mentor junior engineers and contribute to design reviews.

Skills

Verilog

System Verilog

VCS

Verdi

PPA analysis

Design flow understanding

AMBA APB AXI Protocol

RISC/Arm architectures

Startup environment experience

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

FPGA

ASIC

UVM

Job description

TetraMem INC in Fremont is seeking a Lead RTL Designer to spearhead design, simulation, and verification for our innovative ASIC/SoC products. The role demands a deep understanding of digital design methodologies and the ability to mentor junior engineers.

Ideal candidates will possess a master's or PhD with at least 5 years of experience, along with proficiency in Verilog and System Verilog. We offer a competitive compensation package and excellent benefits.