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Platform Recruitment is seeking silicon engineers to own end-to-end design for next-gen ASICs/SoCs. You’ll influence architecture, micro-architecture and RTL sign-off while coordinating with verification, DFT and physical design to achieve top-tier PPA.
Hybrid role with on-site days in the Bay Area and remote considered for the right candidate. Ideal background includes 5+ years in SystemVerilog, Python and C/C++, with hands-on experience in high-performance compute, memory management or
Platform Recruitment is seeking silicon engineers to own end-to-end design for next-gen ASICs/SoCs. You’ll influence architecture, micro-architecture and RTL sign-off while coordinating with verification, DFT and physical design to achieve top-tier PPA.
Hybrid role with on-site days in the Bay Area and remote considered for the right candidate. Ideal background includes 5+ years in SystemVerilog, Python and C/C++, with hands-on experience in high-performance compute, memory management or