Senior SoC Micro-Architect & RTL Designer (Hybrid)

Platform Recruitment

San Francisco (CA)

Hybrid

USD 160,000 - 600,000

Full time

9 hours ago
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Benefits offered by this job

Generous PTO
Medical/dental/vision
401(k) match
Parental leave
Professional development budget
Commute/home-office support

Job summary

Platform Recruitment is seeking silicon engineers to own end-to-end design for next-gen ASICs/SoCs. You’ll influence architecture, micro-architecture and RTL sign-off while coordinating with verification, DFT and physical design to achieve top-tier PPA.

Hybrid role with on-site days in the Bay Area and remote considered for the right candidate. Ideal background includes 5+ years in SystemVerilog, Python and C/C++, with hands-on experience in high-performance compute, memory management or

Qualifications

  • 5+ years of SystemVerilog, Python and C/C++ in chip design and flows.
  • Experience driving ASIC/SoC design from architecture to production silicon.
  • Hands-on with synthesis, equivalence checking, lint and clock-domain-crossing.

Responsibilities

  • Contribute to architecture-to-design methodology across blocks and full-chip design.
  • Own subsystem or chip-level deliverables from micro-architecture through RTL sign-off.
  • Plan reviews for micro-architecture, specs, progress, and timing/area closure.
  • Collaborate with verification, DFT and physical design teams to optimize PPA.

Skills

SystemVerilog
Python
C/C++
Chip design flows

Tools

Synthesis
Equivalence checking
Lint
Timing closure
DFT
Physical design

Job description

Platform Recruitment is seeking silicon engineers to own end-to-end design for next-gen ASICs/SoCs. You’ll influence architecture, micro-architecture and RTL sign-off while coordinating with verification, DFT and physical design to achieve top-tier PPA.

Hybrid role with on-site days in the Bay Area and remote considered for the right candidate. Ideal background includes 5+ years in SystemVerilog, Python and C/C++, with hands-on experience in high-performance compute, memory management or

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