Senior RTL Design Architect for AI ASICs

Anysilicon; Sunnyvale, Northern (CA, KY); Hybrid; USD 210,000 - 320,000; Full time

Job summary

Cerebras Systems, Sunnyvale, CA, is seeking a senior ASIC designer to drive RTL development, manage external vendors, and collaborate across verification, physical design and system teams. The role emphasizes front-end integration, high-speed interfaces, and silicon bring-up, with a hybrid work model in the Bay Area.

Ideal candidates have 8–15 years in complex RTL projects, strong networking and HPC/ML exposure, and a proven track record of successful silicon deliveries.

Qualifications

• Master's degree in Computer Science, Electrical Engineering, or equivalent.
• 8–15 years of experience delivering complex, high-performance RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, or related fields.
• Proven track record of successful silicon projects.
• Experience managing external vendors.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, and Synthesis.
• Manage external ASIC vendors throughout the product development cycle.
• Collaborate with the Physical Design team to achieve design closure and meet PPA goals.
• Work with Design Verification and DFT teams to ensure optimal functional and test coverage.
• Engage with software and system teams to enhance product performance and features.
• Debug silicon-level functional, timing, and power issues during silicon bring-up.

Skills

RTL design

High-speed IO design

Networking stacks

PCIe/Serdes

Python

TCL

Education

Master's degree in CS/EE or equivalent

Tools

Verilog/SystemVerilog

Synthesis

Front End Chip integration

Third-party IP integration

Job description

Cerebras Systems, Sunnyvale, CA, is seeking a senior ASIC designer to drive RTL development, manage external vendors, and collaborate across verification, physical design and system teams. The role emphasizes front-end integration, high-speed interfaces, and silicon bring-up, with a hybrid work model in the Bay Area.

Ideal candidates have 8–15 years in complex RTL projects, strong networking and HPC/ML exposure, and a proven track record of successful silicon deliveries.