Sr. Principal Product Engineer, RTL-GDSII

Cadence; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Cadence in Austin is seeking a Product Engineer in the Digital and Signoff Group to help drive the development of advanced chip design software tools and flows.

You will collaborate with R&D, Application Engineering and product marketing to deliver place-and-route expertise, run PPA benchmarks, analyze timing and power, and develop scripting solutions to optimize design performance.

Qualifications

• Bachelor or Master in EE/CS or equivalent major (Masters level preferred).
• 10+ years hands-on experience with industry standard place-and-route tools (7 years with Master Degree).
• Strong understanding of RTL-GDSII flow.
• Strong understanding of the PDK and DK collaterals.
• Knowledge of Timing and power analysis.
• Good scripting skills.
• Must be legally eligible to work in the US.

Responsibilities

• Provide place-and-route expertise to Cadence customers and internal development teams
• PPA benchmarking on customer and foundry test cases
• Evaluate impact of new features on PPA
• Be a liaison for new features between customer/foundry and R&D development teams
• Develop point solutions with scripting
• Data mining and analysis to uncover PPA limiting issues and identify optimization opportunities

Skills

Place-and-route tools

RTL-GDSII flow

PDK/DK collaterals

Timing and power analysis

Scripting

Data mining

Education

Bachelor or Master in EE/CS

Masters preferred

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

This position presents an exciting opportunity within Cadence’s Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you’ll collaborate closely with R&D, Application Engineering & product marketing teams to help drive the development of advanced chip design software tools. Your responsibilities will include:

• Provide place‑and‑route expertise to both Cadence customers and internal development teams
• PPA benchmarking on customer and foundry test cases
• Evaluate impact of new features on PPA
• Be a liaison for new features between customer/foundry and R&D development teams
• Develop point solutions with scripting
• Data mining and analysis to uncover PPA limiting issues and identify optimization opportunities

Minimum Qualifications

• A Bachelor or Master’s degree in EE/CS or equivalent major (Masters level preferred)
• A minimum of 10 years of hands on experience with any industry standard place‑and‑route tools (7 years with Master Degree)
• A good understanding of the RTL‑GDSII flow
• A good understanding of the PDK and DK collaterals
• Firm understanding of Timing and power analysis
• Good scripting skills
• Must be legally eligible to work in the US

We’re doing work that matters. Help us solve what others can’t.