Tech Lead, AI Connectivity Silicon Design & RTL

Astera Labs; San Jose (CA); In loco; USD 180.000 - 260.000; Tempo pieno

Descrizione del lavoro

Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows.

This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.

Descrizione del lavoro

Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows.

This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.