Principal PD Engineer - Methodology & Flow Automation Lead

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs in San Jose, CA is seeking a Principal Physical Design Engineer-Methodology to define, develop, and maintain reusable physical design flows and automation infrastructure across multi-vendor toolchains (Cadence and Synopsys). You will own the RTL-to-GDSII flow and drive PPA improvements for faster tapeouts.

Qualifications include 8+ years in physical design methodology, strong scripting (Python, Tcl, Perl), and experience with Cadence Innovus/Tempus and Synopsys Fusion

Qualifications

• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below).
• Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows.
• Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation.
• Experience with Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains.
• Ability to build and maintain multi-corner/multi-mode analysis infrastructure.
• Understanding of foundry design rules and enablement kit integration.

Responsibilities

• Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR.
• Own end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains.
• Evaluate and qualify new tool features and flow enhancements to improve PPA and schedule predictability.
• Develop automation scripts and infrastructure for large-scale multi-corner/multi-mode STA and EMIR runs.
• Drive adoption of flow improvements, provide training and documentation.

Job description

Astera Labs in San Jose, CA is seeking a Principal Physical Design Engineer-Methodology to define, develop, and maintain reusable physical design flows and automation infrastructure across multi-vendor toolchains (Cadence and Synopsys). You will own the RTL-to-GDSII flow and drive PPA improvements for faster tapeouts.

Qualifications include 8+ years in physical design methodology, strong scripting (Python, Tcl, Perl), and experience with Cadence Innovus/Tempus and Synopsys Fusion