Manager of Digital Design

Astera Labs; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Flexible time off (US)

Parental leave

401K

Retirement plans

Medical, dental, and vision plans

Job summary

Astera Labs is seeking a Senior Manager/Manager, Digital Design to lead front-end RTL for high-performance PCIe & CXL, UAL, and ethernet devices. You will guide architecture through RTL development, verification, physical design, tape-out, and shipment, ensuring schedules and quality targets are met.

You will mentor 6–8 engineers, establish design checklists, and collaborate with architecture and system teams to translate requirements into robust digital implementations.

Qualifications

• Lead front-end RTL and digital design from requirements through tape-out.
• Drive two complex devices with milestones, decisions, risk tracking, and schedule accountability.
• Mentor a team of 6–8 digital design engineers.
• Define design checklists, gates, and signoff criteria.
• Work with PCIe/CXL/UAL/ethernet requirements to deliver robust designs.

Responsibilities

• Lead digital design execution from requirements through tape-out and production shipment.
• Ensure efficient synthesis, timing closure, and smooth tape-out with cross-functional teams.
• Communicate technical status, tradeoffs, and mitigation plans to engineering leadership.
• Develop scalable design practices and enforce coding standards across the lifecycle.

Skills

RTL development

Front-end digital design

Mentoring

Team leadership

Synthesis and timing

Design verification

Architecture collaboration

Signoff readiness

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s or PhD in Electrical Engineering or Computer Engineering

Tools

Lint

Job description

• As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives
• This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems
• Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment
• Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability
• Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations
• Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out
• Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle
• Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams
• Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration
• Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution
• Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerationsDemonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexityAbility to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operationsStrong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality3-5 years of experience in engineering management or technical leadership in digital IC or ASIC designBachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical fieldExpertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readinessExperience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processesTrack record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programsBuilding design blocks with large physical floorplan sizes is a plusMaster’s or PhD in Electrical Engineering, Computer Engineering, or a related field