Principal NOC & DDR Architect for Next-Gen SoCs

Rivian; United States; On-site; USD 218,000 - 312,000; Full time

Benefits offered by this job

Paid vacation

Paid sick leave

Insurance package

401(k) with match

Employee stock purchase program

Job summary

Rivian seeks a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency.

The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and

Qualifications

• 12+ years of experience in SoC or ASIC architecture with ownership of interconnect and memory subsystem design.
• Deep expertise in NOC architecture, topology, arbitration, QoS, congestion handling, flow control and performance optimization.
• Deep expertise in DDR memory controller architecture and system behavior under real workload conditions.
• Strong understanding of performance, power, area and scalability tradeoffs in high-performance SoCs.
• Experience building architecture models and using data to drive technical decisions.

Responsibilities

• Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs.
• Drive architectural tradeoffs across bandwidth, latency, QoS, coherency, buffering, arbitration, congestion management, power, area, and reliability.
• Own memory subsystem strategy, including DDR controller architecture, scheduling policy, traffic shaping, and system performance optimization.
• Define scalable NOC topology, routing, flow control, bandwidth allocation, and traffic isolation for multi-client SoCs.
• Develop architecture specifications for interconnect and memory subsystems, including interfaces, performance targets, use models, and corner-case behavior.
• Lead performance modeling and analysis to evaluate workload behavior, bottlenecks, utilization, and worst-case traffic scenarios.
• Partner with system architects and domain leads to align subsystem architecture with product requirements and software use cases.
• Work with RTL, verification, and firmware teams to ensure clean architectural intent and measurable requirements.
• Review microarchitecture proposals and implementation choices for alignment with goals.
• Drive debug and root-cause analysis for architecture-related issues during pre-silicon and post-silicon phases.
• Mentor senior engineers and architects and raise architectural rigor across the organization.

Skills

NOC architecture

DDR memory controller

SoC interconnects

Performance modeling

Cross-functional leadership

System-level design

RTL collaboration

Data-driven decisions

Architecture leadership

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field

Job description

Rivian seeks a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency.

The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and