Principal Engineer, DDR & NOC Architecture

Rivian; Plymouth Charter Township (MI); On-site; USD 218,000 - 312,000; Full time

Job summary

Rivian is seeking a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency.

The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of experience in SoC or ASIC architecture with ownership of interconnect and memory subsystem design.
• Deep expertise in NOC architecture, including topology selection, arbitration, QoS, congestion handling, flow control, and performance optimization.
• Deep expertise in DDR memory controller architecture and system behavior under real workload conditions.
• Strong understanding of high-performance SoC design tradeoffs across performance, power, area, and scalability.
• Experience building architecture models and using data to drive technical decisions.
• Strong knowledge of traffic patterns from CPUs, GPUs, AI/ML accelerators, DMA engines, multimedia blocks, and other high-bandwidth clients.
• Proven track record of leading cross-functional technical efforts from concept through silicon.
• Strong written and verbal communication skills with the ability to influence across architecture, design, and product teams.

Responsibilities

• Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs.
• Drive architectural tradeoffs across bandwidth, latency, QoS, coherency, buffering, arbitration, congestion management, power, area, and reliability.
• Own memory subsystem strategy, including DDR controller architecture, scheduling policy, traffic shaping, address mapping, refresh impact, and system performance optimization.
• Define scalable NOC topology, routing, flow control, bandwidth allocation, and traffic isolation mechanisms for multi-client SoCs.
• Develop architecture specifications for interconnect and memory subsystems, including interfaces, performance targets, use models, and corner-case behavior.
• Lead performance modeling and analysis to evaluate workload behavior, bottlenecks, utilization, and worst-case traffic scenarios.
• Partner with system architects and domain leads to align subsystem architecture with product requirements and software use cases.
• Work with RTL, verification, and firmware teams to ensure clean architectural intent, measurable requirements, and efficient implementation.
• Review microarchitecture proposals and implementation choices to ensure consistency with system goals.
• Drive debug and root-cause analysis for architecture-related issues during pre-silicon and post-silicon phases.
• Mentor senior engineers and architects and raise the overall quality of architecture thinking across the organization.

Skills

SoC architecture

NOC architecture

DDR memory controller

Performance modeling

Cross-functional leadership

Architectural specifications

System-level design

Communication skills

Education

BS, MS, or PhD in Electrical Engineering or Computer Engineering

Tools

Architecture modeling tools

Job description

About Rivian

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

We are looking for a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency.

The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and cross-functional technical leadership. They will work closely with system architecture, IP, design, verification, physical design, firmware, and product teams to translate product requirements into robust and production-ready architecture.

Responsibilities

• Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs
• Drive architectural tradeoffs across bandwidth, latency, QoS, coherency, buffering, arbitration, congestion management, power, area, and reliability
• Own memory subsystem strategy, including DDR controller architecture, scheduling policy, traffic shaping, address mapping, refresh impact, and system performance optimization
• Define scalable NOC topology, routing, flow control, bandwidth allocation, and traffic isolation mechanisms for multi-client SoCs
• Develop architecture specifications for interconnect and memory subsystems, including interfaces, performance targets, use models, and corner-case behavior
• Lead performance modeling and analysis to evaluate workload behavior, bottlenecks, utilization, and worst-case traffic scenarios
• Partner with system architects and domain leads to align subsystem architecture with product requirements and software use cases
• Work with RTL, verification, and firmware teams to ensure clean architectural intent, measurable requirements, and efficient implementation
• Review microarchitecture proposals and implementation choices to ensure consistency with system goals
• Drive debug and root-cause analysis for architecture-related issues during pre-silicon and post-silicon phases
• Mentor senior engineers and architects and raise the overall quality of architecture thinking across the organization

Qualifications

Required

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 12+ years of experience in SoC or ASIC architecture with significant ownership of interconnect and memory subsystem design
• Deep expertise in NOC architecture, including topology selection, arbitration, QoS, congestion handling, flow control, and performance optimization
• Deep expertise in DDR memory controller architecture and system behavior under real workload conditions
• Strong understanding of high-performance SoC design tradeoffs across performance, power, area, and scalability
• Experience building architecture models and using data to drive technical decisions
• Strong knowledge of traffic patterns from CPUs, GPUs, AI/ML accelerators, DMA engines, multimedia blocks, and other high-bandwidth clients
• Proven track record of leading cross-functional technical efforts from concept through silicon
• Strong written and verbal communication skills with the ability to influence across architecture, design, and product teams

Preferred qualifications

• Experience with LPDDR and/or DDR architectures used in high-performance and power-constrained systems
• Experience with coherent and non-coherent interconnect fabrics
• Familiarity with cache/memory hierarchy design and system-level performance tuning
• Experience with safety, reliability, ECC, RAS, and functional robustness requirements
• Experience in automotive, AI, edge compute, or other high-compute embedded platforms
• Experience supporting post-silicon tuning and performance characterization

What success looks like

• A clear and scalable NOC and DDR architecture that meets product performance goals without unnecessary implementation risk
• Well-defined architectural specifications that enable efficient execution across design and verification teams
• Early identification of bottlenecks and high-leverage optimizations through modeling and analysis
• Strong alignment across system, hardware, and software stakeholders
• A technically strong team operating with high architectural rigor and clear design intent

Leadership expectations

• Set the technical direction for interconnect and memory subsystem architecture across multiple programs
• Make principled tradeoff decisions grounded in workload behavior and product needs
• Build alignment across diverse engineering teams while maintaining a high bar for technical quality
• Coach and develop senior engineers through reviews, mentoring, and architectural guidance
• Raise organizational capability in performance-driven SoC architecture

Pay Disclosure

The salary range for this role is $218,000 - $312,000 for Palo Alto, CA based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee's position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards.

We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian's 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.

Equal Opportunity

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at [e-mail].

Candidate Data Privacy and Technology

Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes ("Candidate Personal Data"). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law.

Rivian may share your Candidate Personal Data with (i) internal personnel who have a