Principal RTL Design Architect IO & Memory Subsystems

SambaNova, Inc.; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

HSA with employer contribution

Dental and Vision

Well-being benefits (Headspace, Gymday

Employee assistance

Job summary

SambaNova Systems in Austin, TX seeks a Principal Engineer to own IO and memory subsystems for the DataScale platform, driving architecture, RTL, and integration of IP across PCIe, Ethernet, CXL, and HBM. This hands-on role demands strong protocol knowledge and ownership across the product lifecycle.

The ideal candidate has deep RTL expertise, experience with multiple on-chip protocols, and a track record of delivering high-performance AI hardware systems at scale.

Qualifications

• MS in Electrical Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC design.
• Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification.
• Experience with power, performance, or area optimization.
• Experience with two or more on-chip or chip-to-chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe.
• Experience with memory subsystems such as HBM and CXL.
• Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements.
• Clear and effective communicator with a proactive, collaborative approach to problem-solving.

Responsibilities

• Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction.
• Drive feasibility studies and design trade-off analysis to meet PPA constraints.
• Own microarchitecture definition and specification for IO and memory subsystems.
• Deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
• Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
• Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
• Work closely with verification and emulation teams to ensure design validation coverage and quality.
• Collaborate with software and firmware teams to ensure optimal end-to-end solutions.
• Drive cross-functional triage of complex functional and performance issues to root cause and closure.
• Apply engineering best practices including code review, testing, and refactoring.
• Improve design and integration methodology, reuse, and flow scalability.

Skills

Logic design

Microarchitecture

SystemVerilog RTL

Functional verification

Power/Perf/Area optimization

IP evaluation

IEEE/PCIe/Ethernet knowledge

Education

MS in Electrical Engineering or Computer Science

Tools

HBM

CXL

PCIe

Ethernet

UCIe

Job description

SambaNova Systems in Austin, TX seeks a Principal Engineer to own IO and memory subsystems for the DataScale platform, driving architecture, RTL, and integration of IP across PCIe, Ethernet, CXL, and HBM. This hands-on role demands strong protocol knowledge and ownership across the product lifecycle.

The ideal candidate has deep RTL expertise, experience with multiple on-chip protocols, and a track record of delivering high-performance AI hardware systems at scale.