Principal DRAM Circuit Designer, Side S64 Chip Lead

PhantaField; Santa Clara (CA); On-site; USD 210,000 - 290,000; Full time

Job summary

PhantaField is seeking a senior circuit design lead for the Side S64 memory die. You will head the design of the MoS₂-based 2T0C arrays, the read path, and the floorplan that fits on a 126 mm² silicon base.

You’ll work with a contract analog designer for pumps and regulators and report to the CEO. The role requires extensive DRAM/gain-cell experience, mastery of sense amplifiers, retention/refresh design, and floorplanning trade-offs.

Qualifications

• 12+ years of DRAM, eDRAM or gain-cell circuit design, carried through to silicon.
• Expertise in sense amplifiers for very low read currents and their offset statistics.
• Experience with floorplanning trade-offs between array, sense and periphery areas.
• Familiarity with 2D/3D memory stacks and monolithic integration constraints.

Responsibilities

• Lead the circuit design for Side S64 memory die and act as chip lead.
• Design shuttle arrays and inter-tier vias for the shared test shuttle.
• Develop the 2T0C test arrays, 64-tier concepts and read path architectures.
• Specify floorplan constraints: PHY, ECC, refresh within 126 mm² base, or justify larger die.
• Collaborate with layout, memory architect and external contract designer to deliver data.

Skills

DRAM design

Sense amplifiers

Weak-bit SPICE

Wordline drivers

Boosted rails

Retention & refresh design

Floorplanning

Education

B.S./M.S. in EE/CS

Tools

SPICE simulations

PDK/layout tools

VLSI CAD

Job description

Lead the Side S64 memory die from shuttle test arrays to a floorplan that fits.

About us

PhantaField grows memory and logic tiers of 2D MoS₂ transistors on top of finished silicon wafers, at low temperature (below about 450 °C). Van der Waals is our 3D DRAM; its tiers use 28 nm design rules. The first part, Side S64, is a memory die that sits beside a GPU, its tiers stacked on a silicon base. Sophon is our AI chip: 64 tiers grown over 28 nm logic, with 330 GB of DRAM inside the compute array of one 750 mm² die. MoS₂ transistors and a capacitor-less 2T0C memory cell have been measured, and the cell holds data past 1,000 seconds. Both chips are designs, and every chip-level figure here is modeled from those devices. Prof. Chenming Hu, a co-inventor of the FinFET, was our first investor and advises us.

The role

You will lead circuit design for Side S64, our first Van der Waals memory die, and act as its chip lead. The first hard gate is the floorplan: the PHY, 3.38 million sense paths, ECC and refresh have to fit on a 126 mm² silicon base, or the die grows. Before that, you design the 2T0C test arrays and via chains for a test shuttle we share with Sophon. The measured cell pairs a MoS₂ write transistor with a silicon read transistor. The arrays you design are all MoS₂, and they have to work hot. A contract analog designer takes the charge pumps and regulators. You will report to the CEO.

What you'll do

SHUTTLE ARRAYS Design the 2T0C test arrays and the monolithic inter-tier via (MIV) daisy chains for the shared test shuttle, so its silicon tells us retention, via yield and read margin.

TIER CIRCUITS Design the nMOS-only mats (256 × 256 cells plus 4 spare columns), the 16:1 column mux, the tier-select and mat-select gates, and bootstrapped wordline drivers. A tier carries only n-type MoS₂ transistors: no sense amplifier, no p-type device, no logic.

READ PATH Design the global-bitline read path down to current-latch sense amplifiers in the base. Close read margin with up to 47 unselected tier-select gates on each global bitline.

REFRESH AND RAILS Set refresh against measured retention. Specify the charge pumps and the 0.6 V array rail for our contract designer, and review the work.

FLOORPLAN GATE Own the base floorplan with the PDK and layout engineer and the memory architect: PHY, sense paths, ECC and refresh on 126 mm², or a clear case for a bigger die.

What we're looking for

• 12+ years of DRAM, eDRAM or gain-cell circuit design, carried through to silicon
• Sense amplifiers for sub-µA read currents, including offset and its statistics
• Statistical weak-bit SPICE on immature device models
• Wordline drivers, boosted rails and bootstrapped nMOS circuits
• Retention, disturb and refresh design from measured cell data
• Floorplan trade-offs between array, sense and periphery area

Nice to have

• Charge pumps and on-die regulators
• HBM-class or other stacked-DRAM products
• Led a memory tape-out
• Oxide-channel or 2D-channel transistor models
• Monolithic 3D or sequential-integration constraints

Why PhantaField

You set the circuit rules for a memory with 48 tiers (46 data + 2 spare) over one silicon base. A 2T0C cell has been measured; an all-MoS₂ array has not, and you design the first ones. Your first silicon is a shared test shuttle, not a full chip, so real data comes early. You work directly with the engineers who measure the devices and write the tier design rules.

PhantaField is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law. This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.