Principal Design Engineer

Micron Technology, Inc.; San Jose (CA); On-site; USD 176,000 - 298,000; Full time

Job summary

Micron Technology, Inc. in the United States is seeking an experienced engineer to design and optimize TSV interface circuits that connect memory die to logic die, including Rx/Tx channels and timing margin analysis.

You will develop TSV models, define constraints for datapath interfaces, and ensure signal and power integrity across a highly parallel bus, with collaboration across process technology and DTCO teams.

Qualifications

• BS or MS in Electrical Engineering with 8+ years of memory circuit design experience (DRAM, NAND or similar).
• Experience with TSV interface circuits or high-speed memory interfaces (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4).
• Strong knowledge of highly parallel bus performance, clock distribution, skew management and EpB optimization.
• Experience leading complex circuit design projects across multiple blocks and teams.
• Preferred: Hands-on AI to improve design quality and efficiency.
• Preferred: Chip-level PDN optimization.
• Preferred: CMOS device reliability understanding.
• Preferred: CMOS BSIM model and high-speed IO targets.
• Preferred: Signal/power integrity and physical design experience.

Responsibilities

• Design and optimize TSV interface circuits connecting memory die to logic die, including Rx/Tx channels and timing margin analysis.
• Develop and characterize TSV electrical models and define circuit constraints for datapath interface.
• Define and implement signal integrity requirements for TSV channels, including eye margin and crosstalk.
• Define and implement power integrity requirements using TSV for highly parallel IO.
• Design and verify TSV-specific DFT circuits including loopback modes and lane redundancy/remapping.
• Collaborate with process tech and DTCO to optimize TSV rules and layout strategies.
• Develop functional verification plan for TSV interface and internal bus using Verilog regression.
• Design and optimize wide internal parallel data bus across arrays and banks for timing closure.
• Architect data path from page buffer to TSV output, managing parallelism across banks.
• Develop clocking strategies for highly parallel internal bus including wave pipeline and skew management.
• Implement column redundancy and lane repair compatible with high-parallel bus architecture.
• Define timing budgets and perform timing analysis across the datapath under PVT variations.
• Support post-silicon validation, debugging and tape-out revisions.
• Collaborate with packaging to ensure TSV reliability within datapath floorplan.
• Collaborate with project teams on major block interfaces and specs.
• Work with PE to drive silicon experiments and yield improvements.

Skills

TSV design

Memory interface design

Signal integrity

Power integrity

Verilog regression

Clock distribution

PDN optimization

CMOS BSIM model

AI in design

Education

BS or MS in Electrical Engineering

Tools

Verilog

BSIM model

Job description

Responsibilities

• Design and optimize TSV (Through-Silicon Via) interface circuits connecting memory die to logic die including Rx/Tx circuit for internal TSV channels, impedance matching and timing margin analysis.
• Develop and characterize TSV electrical models and define circuit design constraints for datapath interface.
• Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis.
• Define and implement power integrity requirements using TSV for highly parallel IO and array operations.
• Design and verify TSV-specific DFT (Design for Testability) circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic.
• Collaborate with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath.
• Develop and implement functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression.
• Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus.
• Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks.
• Develop clocking and synchronization strategies for the highly parallel internal bus including wave pipeline design, clock distribution, and skew management.
• Implement and optimize column redundancy and lane repair schemes compatible with HBM like highly parallel bus architecture.
• Define timing budgets and perform timing analysis across the full internal datapath under PVT variations.
• Support post-silicon validation, debug and correlation activities; identify schematic edits and drive vital tape-out revisions.
• Collaborate with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan.
• Collaborate with project integration and other functional teams in design on specifications of major block interfaces.
• Work with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging.
• Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations.

Qualifications

• BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies.
• Experience with TSV interface circuit design or high-speed memory interface design (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity.
• Strong knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB (Energy per Bit) optimization in the context of 3D-stacked memory architectures.
• Experience managing sophisticated circuit design projects spanning multiple functional blocks and multi-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design and non-design customers.
• Preferred: Hands on experience in applying AI to improve quality of design and efficiency.
• Preferred: Experience at chip level PDN optimization.
• Preferred: Comprehensive understanding of CMOS device and device reliability.
• Preferred: Comprehensive understanding of CMOS BSIM model and CMOS target for high-speed IO operation.
• Preferred: Experience with signal/power integrity, power delivery network design, physical design.

Benefits and Compensation

Micron offers a competitive salary range of $176,000.00 - $298,000.00 per year plus benefits, bonuses and equity.

Additional compensation may include benefits, bonuses and equity. Salary range reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Individual pay is determined by work location and other factors.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. It includes medical, dental, and vision plans; income protection programs; paid family leave; paid time-off and paid holidays.

Equal Opportunity Employment

Micron is proud to be an equal-opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Micron does not charge candidates any recruitment fees or unlawfully collect any payment from candidates.