Senior Characterization and Test Engineer

PhantaField; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

PhantaField in Santa Clara, CA seeks a Senior Characterization and Test Engineer to turn wafers into data. You will set up the lab, run 2T0C style memory tests, measure retention and read margin across temperatures, and ensure test plans align with device and modeling goals.

You will own probe and hot-chuck operations, correlate measurements with SPICE, and collaborate with the device and modeling lead to deliver reliable silicon data for the Sophon and Side S64 programs.

Qualifications

• 6+ years of parametric and memory characterization on wafer
• Low-current, leakage and retention measurements at temperature
• Probe stations, hot chucks and source-measure instruments
• Python for instrument control and data analysis
• Correlating measured data with SPICE or compact models
• Test plans that someone else can run and repeat

Responsibilities

• LAB SETUP Set up the probe station with a hot chuck, in our own space or on rented time, and the reliability bench beside it.
• CELL DATA Measure retention, variability and read margin on 2T0C cells and small arrays from 25 to 105 °C.
• SHUTTLE SILICON Measure the MIV daisy chains and 2T0C test arrays from the shared shuttle.
• MODEL LOOP Correlate silicon to SPICE and hand clean data sets to device modeling and the design kit.
• TEST PLAN Write the S64 sort, burn-in and early reliability plan with the test house.

Skills

Python for instrument control

Wafer memory characterization

Measurement at temperature

Data analysis

Tools

Probe stations

Hot chucks

Source-measure instruments

SPICE/Compact models

Job description

Senior Characterization and Test Engineer

Measure the next memory cells and the first test silicon, hot, and set up the lab.

About us

PhantaField grows memory and logic tiers of 2D MoS₂ transistors on top of finished silicon wafers, at low temperature (below about 450 °C). Van der Waals is our 3D DRAM; its tiers use 28 nm design rules. The first part, Side S64, is a memory die that sits beside a GPU, its tiers stacked on a silicon base. Sophon is our AI chip: 64 tiers grown over 28 nm logic, with 330 GB of DRAM inside the compute array of one 750 mm² die. MoS₂ transistors and a capacitor-less 2T0C memory cell have been measured, and the cell holds data past 1,000 seconds. Both chips are designs, and every chip-level figure here is modeled from those devices. Prof. Chenming Hu, a co-inventor of the FinFET, was our first investor and advises us.

The role

You turn wafers into data. First comes an all-MoS₂ 2T0C cell, measured at 25, 85, 95 and 105 °C on a rail of 1 V or less. Then the test shuttle we share between the memory and Sophon: retention, monolithic inter-tier via (MIV) daisy-chain yield, read margin, and how closely silicon matches SPICE (the bar is within ±15%). You own the probe and hot-chuck setup and the reliability bench. Later you write the S64 sort and burn-in plan with a test house, so every part is tested before it meets the GPU. You will report to the device and modeling lead.

What you'll do

LAB SETUP Set up the probe station with a hot chuck, in our own space or on rented time, and the reliability bench beside it.

CELL DATA Measure retention, variability and read margin on 2T0C cells and small arrays from 25 to 105 °C.

SHUTTLE SILICON Measure the MIV daisy chains and 2T0C test arrays from the shared shuttle.

MODEL LOOP Correlate silicon to SPICE and hand clean data sets to device modeling and the design kit.

TEST PLAN Write the S64 sort, burn-in and early reliability plan with the test house.

What we're looking for

• 6+ years of parametric and memory characterization on wafer
• Low-current, leakage and retention measurements at temperature
• Probe stations, hot chucks and source-measure instruments
• Python for instrument control and data analysis
• Correlating measured data with SPICE or compact models
• Test plans that someone else can run and repeat

Nice to have

• DRAM test on memory ATE
• Reliability setups: retention, disturb, HTOL
• Failure analysis
• Thin-film or 2D-material transistor measurement

Why PhantaField

Each step of this program waits on a measurement: a cell that holds data hot, a via chain that yields, a model that matches silicon. You take those measurements. You also choose how the bench is built and run, because there is no bench yet.

PhantaField is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law. This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.