Principal Tier Process Integration Engineer

PhantaField; Santa Clara (CA); On-site; USD 240,000 - 400,000; Full time

Job summary

PhantaField seeks a Principal Tier Process Integration Engineer to validate and optimize MoS2 tier growth on finished logic wafers while preserving wafer integrity. You will define the base back-end metal, per-tier flow, and tier isolation test vehicles, working closely with the CEO and device lead at the integration site.

You will lead thermal-history twins, assess electromigration and TDDB, and develop costed mask strategies.

Qualifications

• 12+ years of back-end-of-line or low-temperature process integration experience.
• Proven yield and defect engineering background, including defect density per layer.
• Experience with reliability checks (EM, TDDB, threshold shift) on full-flow wafers.
• Experience collaborating with a foundry or research fab as an external customer.
• Ability to write a costed, per-tier process flow and mask count.

Responsibilities

• Thermal Twin: Run full-flow logic wafers through tier steps and re-check reliability metrics.
• Back-end metal: Select base metal (W or Ru with low-k) and supplier sources.
• Tier flow: Write per-tier process flow, count masks and cost them from quotes.
• Isolation: Build tier-isolation test vehicle with injected defects.
• Defects: Measure defect density per tier against the yield model.

Skills

Integration experience

Yield engineering

Reliability testing

Foundry collaboration

Process flow design

Tools

MOCVD

ALD

Job description

Principal Tier Process Integration Engineer

Prove that MoS₂ tiers can be grown on finished logic wafers without harming them

About us

PhantaField designs chips built by growing memory and logic tiers of 2D semiconductors such as MoS₂, a few atoms thick, on top of finished silicon wafers at low temperature. Van der Waals is our 3D DRAM family, and Side S64 goes first: a memory die that sits beside the GPU, where HBM sits today. Sophon is our AI chip: one 750 mm² die with 64 tiers grown over 28 nm logic, holding 330 GB of DRAM inside the compute array. MoS₂ transistors have been measured, and so has a capacitor-less 2T0C memory cell with a MoS₂ write transistor that holds data past 1,000 seconds. Van der Waals and Sophon are designs: every chip-level figure here is modeled from those measurements. Prof. Chenming Hu, co-inventor of the FinFET, was our first investor and advises us.

The role

Our tiers are designed to be grown on finished logic wafers, so the first question is whether the wafer underneath comes through intact. You will answer it with a thermal-history twin, then choose the base back-end metal, write the per-tier flow and build the test vehicle for tier isolation. You will spend extended time at the integration site we choose. You are our first integration engineer, you report to the CEO, and you work closely with the device lead. This process know-how is core to the company.

What you'll do

THERMAL TWIN Take full-flow logic wafers through every tier step in the real growth ambient, then re-check electromigration, TDDB, threshold voltage and sense-amp offset.

BACK-END METAL Choose the base back-end metal, W or Ru against Cu with low-k, together with where the base wafers come from.

TIER FLOW Write the per-tier process flow, count its masks and build its cost from quotes, replacing the placeholder we use today.

ISOLATION Build the tier-isolation test vehicle, with injected defects.

DEFECTS Measure defect density per tier against the yield model.

What we're looking for

• Integration: 12+ years of back-end-of-line or low-temperature process integration.
• Yield: You have done yield and defect engineering, including defect density per layer.
• Reliability: You have checked EM, TDDB and threshold shift on full-flow wafers.
• Fabs: You have worked with a foundry or research fab as an outside customer.
• Flows: You have written a process flow and costed its masks and steps.
• On site: You are ready to spend extended time at the integration site.

Nice to have

• 2D-material or monolithic 3D integration.
• DRAM cell integration.
• MOCVD or ALD on device wafers.

Why PhantaField

The thermal budget on a finished back end is the question the whole approach rests on, and you answer it first. You decide the base metal and the per-tier flow, choices that are still open. The work feeds both the memory and the AI chip.

PhantaField is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), physical or mental disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law. This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.