Senior PDK & Tier Layout Engineer for 2D MoS2 Chips

PhantaField; Santa Clara (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

PhantaField seeks an experienced layout and PDK engineer to own rule decks and design kits for our first 2D-MoS₂ memory tiers. You will lay out the shuttle structures, automate tier tiling, and keep rule decks up to date as data flows in from process teams.

You report to the device and modeling lead and collaborate daily with the DRAM circuit lead to ensure accurate sign-off and tape-in readiness. This role is based in Santa Clara, CA.

Qualifications

• 7+ years of PDK development or custom memory layout.
• Experience writing Calibre or PVS rule decks for DRC/LVS.
• Experience with memory arrays or bitcells at tight pitch.
• Strong scripting abilities (SKILL, Python).
• Ability to translate process data into design rules with engineers.
• Experience taking a layout through sign-off to tape-in.

Responsibilities

• Own the tier rule decks: channel, gate, contacts, 90 nm-pitch MIVs and the via towers.
• Package the compact models and corners into a kit designers can use, with a reference mat and cell.
• Lay out the shuttle's 2T0C arrays and MIV daisy chains for tape-in.
• Lay out one tier and tile it by script. One fixed array on one die does not need a memory compiler.
• Run DRC and LVS against both the silicon base kit and the tier kit.

Skills

PDK development

Custom memory layout

Rule decks Calibre

Rule decks PVS

Scripting (SKILL, Python)

Tape-in process knowledge

Tools

Calibre

PVS

SKILL

Python

Job description

PhantaField seeks an experienced layout and PDK engineer to own rule decks and design kits for our first 2D-MoS₂ memory tiers. You will lay out the shuttle structures, automate tier tiling, and keep rule decks up to date as data flows in from process teams.

You report to the device and modeling lead and collaborate daily with the DRAM circuit lead to ensure accurate sign-off and tape-in readiness. This role is based in Santa Clara, CA.