Senior Tier PDK and Layout Engineer

PhantaField; Santa Clara (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

PhantaField seeks an experienced layout and PDK engineer to own rule decks and design kits for our first 2D-MoS₂ memory tiers. You will lay out the shuttle structures, automate tier tiling, and keep rule decks up to date as data flows in from process teams.

You report to the device and modeling lead and collaborate daily with the DRAM circuit lead to ensure accurate sign-off and tape-in readiness. This role is based in Santa Clara, CA.

Qualifications

• 7+ years of PDK development or custom memory layout.
• Experience writing Calibre or PVS rule decks for DRC/LVS.
• Experience with memory arrays or bitcells at tight pitch.
• Strong scripting abilities (SKILL, Python).
• Ability to translate process data into design rules with engineers.
• Experience taking a layout through sign-off to tape-in.

Responsibilities

• Own the tier rule decks: channel, gate, contacts, 90 nm-pitch MIVs and the via towers.
• Package the compact models and corners into a kit designers can use, with a reference mat and cell.
• Lay out the shuttle's 2T0C arrays and MIV daisy chains for tape-in.
• Lay out one tier and tile it by script. One fixed array on one die does not need a memory compiler.
• Run DRC and LVS against both the silicon base kit and the tier kit.

Skills

PDK development

Custom memory layout

Rule decks Calibre

Rule decks PVS

Scripting (SKILL, Python)

Tape-in process knowledge

Tools

Calibre

PVS

SKILL

Python

Job description

Own the first design kit for 2D-semiconductor tiers and lay out our test shuttle.

About us

PhantaField grows memory and logic tiers of 2D MoS₂ transistors on top of finished silicon wafers, at low temperature (below about 450 °C). Van der Waals is our 3D DRAM; its tiers use 28 nm design rules. The first part, Side S64, is a memory die that sits beside a GPU, its tiers stacked on a silicon base. Sophon is our AI chip: 64 tiers grown over 28 nm logic, with 330 GB of DRAM inside the compute array of one 750 mm² die. MoS₂ transistors and a capacitor-less 2T0C memory cell have been measured, and the cell holds data past 1,000 seconds. Both chips are designs, and every chip-level figure here is modeled from those devices. Prof. Chenming Hu, a co-inventor of the FinFET, was our first investor and advises us.

The role

No design kit exists yet for our 2D-semiconductor tiers. An outside design-enablement firm writes version 1 of the rule decks, and you own them from there. You lay out the structures for the test shuttle we share between the memory and Sophon. Then you lay out one tier and tile it by script, because there is no memory compiler for this. As process data comes in, you keep the rules current. You will report to the device and modeling lead and work every day with the DRAM circuit lead.

What you'll do

RULE DECKS Own the tier rule decks: channel, gate, contacts, 90 nm-pitch monolithic inter-tier vias (MIVs) and the via towers.

DESIGN KIT Package the compact models and corners into a kit designers can use, with a reference mat and cell.

SHUTTLE LAYOUT Lay out the shuttle's 2T0C arrays and MIV daisy chains for tape-in.

TIER LAYOUT Lay out one tier and tile it by script. One fixed array on one die does not need a memory compiler.

SIGN-OFF Run DRC and LVS against both the silicon base kit and the tier kit.

What we're looking for

• 7+ years of PDK development or custom memory layout
• Writing Calibre or PVS rule decks for DRC and LVS
• Custom layout of memory arrays or bitcells at tight pitch
• Scripted layout generation (SKILL, Python or similar)
• Turning process data into design rules with device engineers
• Taking a layout through sign-off to tape-in

Nice to have

• BEOL and via rules
• Parasitic extraction setup
• Monolithic 3D or sequential-integration layout
• Packaging compact models and defining corners

Why PhantaField

You own the rules the first designs on this process are drawn to. Every structure on the shuttle passes your decks. When the process changes, you decide how the rules change with it.

PhantaField is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law. This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.