Staff Architect, Sophon AI ASIC

PhantaField; Santa Clara (CA); On-site; USD 190,000 - 290,000; Full time

Job summary

PhantaField seeks an experienced architect to own the Sophon spec and its performance model. You will validate mappings, define banking and host I/O layouts, and shape the die that fits the 26 × 33 mm exposure field.

You will collaborate with RTL teams, fold coupon data into architecture, and decide on EDA tool strategy to keep the project on schedule for a 750 mm² tape-out.

Qualifications

• 10+ years of accelerator or compute-in-memory architecture.
• Cycle-level and analytical performance modeling.
• Transformer inference: prefill, decode, KV cache and batching.
• Memory hierarchy design for accelerators.
• Writing specs that RTL teams build from.

Responsibilities

• Own the spec: tile, banking, on-die network, tier controller, host I/O and scale-out.
• Turn our in-house simulator and model-to-tile mapper into a validated performance model, with honest prefill and decode behavior.
• Set the limits first silicon must meet against the performance model, before that silicon exists.
• Fold the co-integration coupon results into the architecture.
• Decide whether our in-house EDA tools stay in the flow or give way to commercial ones.

Skills

Accelerator architecture

Performance modeling

RTL comprehension

Tile-level design

Co-design with compiler/mapper

Tools

In-house EDA tools

Job description

Own the Sophon spec of record and the performance model that backs it.

About us

PhantaField grows memory and logic tiers of 2D MoS₂ transistors on top of finished silicon wafers, at low temperature (below about 450 °C), for two chips: Van der Waals 3D DRAM and Sophon, our AI chip. Sophon stacks 64 tiers over 28 nm logic, with 330 GB of DRAM inside the compute array of one 750 mm² die. Its 32 logic tiers of compute-in-memory tiles alternate with 32 memory tiers, and weights move between them through vertical vias, never over the on-die network. MoS₂ transistors and a capacitor-less 2T0C memory cell have been measured, and the cell holds data past 1,000 seconds. Both chips are designs, and every chip-level figure here is modeled from those devices. Prof. Chenming Hu, a co-inventor of the FinFET, was our first investor and advises us.

The role

The Sophon spec has open questions, and you close them: how 330 GB maps onto per-tile banking, the host interface, and a die shape that fits the 26 × 33 mm exposure field. Today the RTL is a planar stand-in, and our performance simulator and mapper are in-house and not yet validated against silicon. Data from a co-integration coupon on our shared test shuttle comes in soon after you start. You fold it in, so the spec and the performance model are ready for the full 750 mm² tape-out. You will report to the CEO.

What you'll do

SPEC OF RECORD Own the spec: tile, banking, on-die network, tier controller, host I/O and scale-out.

PERFORMANCE MODEL Turn our in-house simulator and model-to-tile mapper into a validated performance model, with honest prefill and decode behavior.

SILICON LIMITS Set the limits first silicon must meet against the performance model, before that silicon exists.

SHUTTLE DATA Fold the co-integration coupon results into the architecture.

TOOLS Decide whether our in-house EDA tools stay in the flow or give way to commercial ones.

What we're looking for

• 10+ years of accelerator or compute-in-memory architecture
• Cycle-level and analytical performance modeling
• Transformer inference: prefill, decode, KV cache and batching
• Memory hierarchy design for accelerators
• Writing specs that RTL teams build from
• Reading and reviewing SystemVerilog RTL

Nice to have

• Memory-centric architectures
• Took a large-die chip to silicon
• Monolithic 3D or multi-tier integration constraints
• Compiler or mapper co-design

Why PhantaField

Sophon keeps its 330 GB inside the compute array, so the hard questions are banking, refresh, heat, and a die that fits one exposure field. You own those answers for the whole chip.

PhantaField is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law. This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.