Lead DRAM Circuit Designer for Van der Waals Memory Die

PhantaField; Santa Clara (CA); On-site; USD 210,000 - 290,000; Full time

Job summary

PhantaField is seeking a senior circuit design lead for the Side S64 memory die. You will head the design of the MoS₂-based 2T0C arrays, the read path, and the floorplan that fits on a 126 mm² silicon base.

You’ll work with a contract analog designer for pumps and regulators and report to the CEO. The role requires extensive DRAM/gain-cell experience, mastery of sense amplifiers, retention/refresh design, and floorplanning trade-offs.

Qualifications

• 12+ years of DRAM, eDRAM or gain-cell circuit design, carried through to silicon.
• Expertise in sense amplifiers for very low read currents and their offset statistics.
• Experience with floorplanning trade-offs between array, sense and periphery areas.
• Familiarity with 2D/3D memory stacks and monolithic integration constraints.

Responsibilities

• Lead the circuit design for Side S64 memory die and act as chip lead.
• Design shuttle arrays and inter-tier vias for the shared test shuttle.
• Develop the 2T0C test arrays, 64-tier concepts and read path architectures.
• Specify floorplan constraints: PHY, ECC, refresh within 126 mm² base, or justify larger die.
• Collaborate with layout, memory architect and external contract designer to deliver data.

Skills

DRAM design

Sense amplifiers

Weak-bit SPICE

Wordline drivers

Boosted rails

Retention & refresh design

Floorplanning

Education

B.S./M.S. in EE/CS

Tools

SPICE simulations

PDK/layout tools

VLSI CAD

Job description

PhantaField is seeking a senior circuit design lead for the Side S64 memory die. You will head the design of the MoS₂-based 2T0C arrays, the read path, and the floorplan that fits on a 126 mm² silicon base.

You’ll work with a contract analog designer for pumps and regulators and report to the CEO. The role requires extensive DRAM/gain-cell experience, mastery of sense amplifiers, retention/refresh design, and floorplanning trade-offs.