Principal/ Sr.Principal Digital Design Engineer

Astera Labs; San Jose (CA); Presencial; USD 185.000 - 230.000; Jornada completa

Descripción de la vacante

Astera Labs seeks a Principal Digital Design Engineer to architect and implement next‑generation digital designs for high‑performance AI connectivity solutions.

You will own blocks from micro‑architecture through silicon bring‑up, driving RTL and coordinating with verification, physical design, and DFT teams to deliver production‑quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

Formación

• Bachelor's degree in Electrical Engineering or equivalent.
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis.
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation.
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar.
• Production experience with advanced CMOS nodes (≤7nm).
• Proficiency with Cadence and/or Synopsys digital design flows.

Responsabilidades

• Design ownership and implement complex digital blocks and subsystems from micro-architecture to RTL.
• Drive timing closure and implement DFT features for performance.
• Lead production-ready designs with quality and schedule accountability.
• Collaborate with verification teams to develop test plans and achieve coverage.
• Own third-party IP integration and block-level verification through sign-off.
• Mentor junior engineers and drive CAD automation improvements.

Conocimientos

RTL coding

Timing closure

DFT implementation

Synthesis

Cadence flows

Verification collaboration

IP integration

Mentoring

Hardware debugging

Educación

Bachelor's degree in Electrical Engineering

Herramientas

Cadence tools

Synopsys tools

Descripción del empleo

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Digital Design Engineer

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

Key Responsibilities

• Design Ownership & Execution
  • Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
  • Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
  • Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
  • Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
  • Own third-party IP integration and block-level verification through sign-off
  • Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
  • Mentor junior engineers to develop their technical skills and expertise
  • Actively contribute to the development and improvement of silicon development processes
  • Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.